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  1. Genesys 2: RGMII Rx DDR shift

    Asked by escou64,

    0 votes
    0 answers

  2. PMOD AD1 FPGA bitstream genatation issues

    Asked by amilashanaka,

    0 votes
    1 answer

  3. Arty-Z7-20 ethernet PHY failure, and build quality issues

    Asked by cogans,

    0 votes
    1 answer

  4. My basys 3 don’t Turn on

    Asked by Vanessa,

    0 votes
    1 answer

  5. How to apply a phase to form an output sine wave in the Cordic IP block?

    Asked by loser,

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    1 answer

5,448 questions in this forum

  1. Some questions about API in DMGR

    Asked by erick.chang,

    0 votes
    1 answer

  2. Interfacing FT2232 with Spartan 7

    Asked by SCguy,

    0 votes
    1 answer

  3. JTAG-HS3 setup

    Asked by ekallal,

    0 votes
    1 answer

  4. Can't select Basys3 board in Vivado 2023.1

    Asked by Trevorskie,

    0 votes
    11 answers

  5. Issue with custom UART, looking for debugging paths

    Asked by sweeneyal,

    0 votes
    3 answers

  6. Nexys-4 board, confused about xdc file and migration to Nexys-4 DDR/Nexys A7-100t

    Asked by dravenchrist,

    0 votes
    1 answer

  7. Genesys2 FMC complete pinout missing in .xdc file

    Asked by DanielMtz,

    0 votes
    2 answers

  8. Zedboard gerber files needed!

    Asked by Leon18,

    0 votes
    5 answers

  9. The output waveform of the Eclypse Z7 Low-Level Low-Pass Filter Demo is not same as the reference example projects

    Asked by omara,

    0 votes
    0 answers

  10. NetFPGA-7 1G CML

    Asked by Duy Trung,

    0 votes
    1 answer

  11. Eclypse Z7 zmodlib undefined reference error

    Asked by BFritz,

    0 votes
    2 answers

  12. Eclypse 1410 ADC constraint file name mismatch issue, IO placement Infeasible

    Asked by Xband,

    0 votes
    3 answers

  13. Trying to modify the constraints file to accommodate 2 ADC 1410 modules, do not see how the schematic and baseline files match?

    Asked by Xband,

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    12 answers

  14. NetFPGA-SUME bom file

    Asked by nvdatx1,

    0 votes
    2 answers

  15. I2C interfacing with Zybo Z7020

    Asked by Niranjana,

    0 votes
    0 answers

  16. CMOD A7 15T: unable to start from Flash

    Asked by Guest,

    0 votes
    17 answers

  17. Arty Z7 user manual or working steps

    Asked by Prakash,

    0 votes
    3 answers

  18. How can I store data in Basys 3 and use it in my DUT

    Asked by 222mzb,

    0 votes
    1 answer

  19. AXI_ZmodADC1410_v1_0.dcp is not suitable for use with incremental synthesis for this design. Please regenerate the checkpoint for this design with -incremental_synth

    Asked by Xband,

    0 votes
    1 answer

  20. Implementation of GNSS receiver based on MAX2769 and ZedBoard

    Asked by Jozef,

    0 votes
    14 answers

  21. Reset signal as a clock signal

    Asked by NotRandom,

    0 votes
    3 answers

  22. Genesys 2 HDMI Demo

    Asked by DBanks60,

    0 votes
    2 answers

  23. Zybo Z7 Pcam 5C Demo

    Asked by Magdalene Ratna,

    0 votes
    0 answers

  24. Unable to FLASH QSPI. Vivado Rev. 2022.1 5ev eval board

    Asked by Luigee,

    1 vote
    9 answers

  25. [BD 41-238] Port/Pin property POLARITY does not match between /clk_wiz/reset(ACTIVE_HIGH) and /processing_system7_0/FCLK_RESET0_N(ACTIVE_LOW)

    Asked by Xband,

    0 votes
    4 answers
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