Arty-Z7-20 ethernet PHY failure, and build quality issues

[cogans]

I have ordered 4 ARTY-Z7-20 boards in the last few years.  I bought 2 a month ago (Rev D), and 2 several years ago (Rev B).

There seem to be some build quality issues, or perhaps someone can explain why out of *Four Arty-Z7 boards*, *NONE* of them work completely.  They fail in 3 different ways:  OTP memory doesn't work, ethernet PHY doesn't work, or the ARM program will not launch at all.

I developed a simple telnet interface running on the ARM (from a simple TCP echo example), utilizing lwip library and the RJ45 network connection.  It echoes a few commands and gets some data from the FPGA.  However, all 4 boards have problems.

Only board #1 can successfully run the telnet program on the ARM.  However, this board cannot read the OTP memory, which has a unique ID that I need to read (EUI-48ID).

Boards #2 and #3 cannot run the telnet program.  They fail during the ethernet PHY autonegotiation, with the message: 

Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
Phy setup error
Phy setup failure init_emacps

Board #4 immediately fails after programming (via the PROG USB) with a strange error in a VITIS popup dialog:

Error while launching program:
Memory write error at 0x109000.  MMU section translation fault

I am extremely frustrated by this.  With 4 boards, none of them work 100%, each with different failure modes.  Can someone please explain?  Otherwise, it seems Digilent has a serious problem with build quality and board testing.

Edited April 24 by cogans
format

[JRys]

I have a Rev D Arty Z7. After reading your post, I walked through the Zynq Server guide using Vivado 2023.1 and did not experience the same trouble. Older Arty Z7 boards use an older Rev Realtek PHY chip and should work as is with Vivado, whereas new boards require a patch to the LWIP Library. To patch your system, use the attached file and overwrite: C:\Xilinx\Vitis\2023.1\data\embeddedsw\ThirdParty\sw_services\lwip213_v1_0\src\contrib\ports\xilinx\netif\xemacpsif_physpeed.c, assuming you have 2023.1. 

Could you walk through the Zynq Server guide using one of your new boards to see if you can get the echo server working with the update to the LWIP Library? 

xemacpsif_physpeed.c