How to apply a phase to form an output sine wave in the Cordic IP block?

[loser]

I am a novice FPGA and Vivado user and I am facing some problems. I need to apply a Cordic phase to get an output signal. To do this, I added Cordic in Vivado 2019.1 and selected its "Sin and Cos" mode of operation. I've been studying testbench for a long time, but I still haven't figured out what I need to change in order to supply a phase input and get a sine wave output. And I also don't understand why the input is a sine and cosine, and the output is a signal of an incomprehensible shape. Inputs: s_axis_cartesian_tdata[31:0], s_axis_phase_tdata[15:0]. Output: m_axis_dout_tdata[31:0].
I hope someone can help.

[artvvb]

Hi @loser

Try pushing some known points in and see what the result is - change the testbench input and see what happens. Below is a testbench that just counts through all bit values that phase could be, using your IP settings:

module cordic;
    reg clk;
    initial begin
        clk = 0;
        forever #0.5 clk = ~clk;
    end
    reg [15:0] din;
    wire [31:0] dout;
    wire dout_valid;
    
    initial begin
        din <= 0;
        forever @(posedge clk) din <= din + 1;
    end
    
    cordic_0 dut (
        .aclk(clk),
        .s_axis_phase_tdata(din),
        .s_axis_phase_tvalid(1'b1),
        .m_axis_dout_tdata(dout),
        .m_axis_dout_tvalid(dout_valid)
    );
endmodule

Waveform Style -> Analog Settings for dout:

Radix -> Real Settings for dout:

Thanks,

Arthur