Eclypse 1410 ADC constraint file name mismatch issue, IO placement Infeasible

[Xband]

Thjis is the first time this warning has happened but now it seems none of the names for my constraint file match?  I'm not sure actually what they need to match, any insight?  This project is using two 1410 ADC's.  

Now getting that I don't have enough ports. This process is feeling like a slot machine, hopefully will get better. 

Thanks for any help.  This process is very slow, hopefully will get through these errors soon.  

This project should mimic the zmod scope using 2 1410 ADC zmods.  I don't think I've done anything that crazy. 

Thanks

 

Edited September 7, 2023 by Xband
update

[artvvb]

Hi @Xband

The AXI port names in the list of unplaced ports make me think that you have the wrong top module. Please make sure that the block design HDL wrapper is set as the top module for your project in the sources pane. It should be bolded, like here:

You can change which module is selected as the top module by right-clicking on the one you want and selecting "Set as Top".

Thanks,

Arthur

[Xband]

@artvvb,

I think that was the problem!  Good call.  I have a bit of a mess in that sources window for some reason, bringing that to the top now produced a successful synthesized design with only a few errors.  I took a day off on the project, thanks for that reply on Thursday!

Jim

 

[Synth 8-6895] The reference checkpoint C://GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/utils_1/imports/synth_1/AXI_ZmodADC1410_v1_0.dcp is not suitable for use with incremental synthesis for this design. Please regenerate the checkpoint for this design with -incremental_synth switch in the same Vivado session that synth_design has been run. Synthesis will continue with the default flow
 

4 like this, 

[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports,  port sADC_Sclk_1 can not be placed on PACKAGE_PIN T18 because the PACKAGE_PIN is occupied by port sADC_Sclk_0. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["C://GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/constrs_1/new/1410ADCmod.xdc":76]
 

[artvvb]

Posted a project  and some constraints over here: 

 

Quote

port sADC_Sclk_1 can not be placed on PACKAGE_PIN T18 because the PACKAGE_PIN is occupied by port sADC_Sclk_0

Just means that you are trying to use the same location constraint for two different pins - more incorrect constraints. sADC_Sclk_1 should probably be at AA13.