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Nexys-4 board, confused about xdc file and migration to Nexys-4 DDR/Nexys A7-100t



Apologies, I am still a newbie and have not played with FPGAs for years.


I have a Nexys-4 FPGA board, and does not have the "Nexys-4 DDR" label like some other boards. I am confused what "migration" means to Nexys-4 DDR or Nexys A7-100T. My assumption was it is an upgrade to the internal board, so I tried using .xdc files for Nexys-4-DDR-MASTER and Nexys-A7-100T for a simple VHDL code for turning LEDs on, but neither .xdc files work and it does not look like the pin names to the LEDs are being mapped correctly?

For example, for nexys-4 ddr, led[0] net pin, which does not work:

set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]

But the nexys-4 xdc constraints file I had used years ago still work:

## LEDs
##Bank = 34, Pin name = IO_L24N_T3_34,						Sch name = LED0
set_property PACKAGE_PIN T8 [get_ports {led[0]}]					
	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]

I am using Vivado 2023.1.1. I am not sure if this migration process is something I can do with the board I currently have, or do I have to purchase a physically newer board?

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Hi @dravenchrist

The Nexys 4 and Nexys 4 DDR aren't pin-compatible, which means that any designs for one board need to have their constraints updated to match the new pin locations. The FPGAs on both boards are physically connected to the other components on the PCBs in different ways, and the tools need to be informed of this via the constraints. The Nexys A7 and Nexys 4 DDR should be the same as each other though. Check out the following resources:

The Nexys 4 should be supported just fine in recent versions of Vivado.



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