Trying to modify the constraints file to accommodate 2 ADC 1410 modules, do not see how the schematic and baseline files match?

Xband · July 12, 2023

Below I modified all of the DAC settings to "dADC", I'm a rookie just trying to make this work for the first time.

Any comments on correlating the B port to the ADC module could be helpful, thanks,

PHY
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L12P_T1_MRCC Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }];

# Syzygy Port A
set_property IOSTANDARD DIFF_SSTL18_I [get_ports -filter { name =~ adcClkIn* }]
set_property -dict { PACKAGE_PIN N20 } [get_ports { adcClkIn_n_0 }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
set_property -dict { PACKAGE_PIN N19 } [get_ports { adcClkIn_p_0 }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
set_property SLEW SLOW [get_ports -filter { name =~ adcClkIn* }]

set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingL_0 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingH_0 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingL_0 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingH_0 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainL_0 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainH_0 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainL_0 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainH_0 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS18 } [get_ports { sRelayComL_0 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS18 } [get_ports { sRelayComH_0 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]

set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Sclk_0 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS18 } [get_ports { sADC_SDIO_0 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports { sADC_CS_0 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]

set_property -dict { PACKAGE_PIN M22 } [get_ports { adcSync_0 }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ adcSync* }]
set_property DRIVE 4 [get_ports -filter { name =~ adcSync* }]
set_property SLEW SLOW [get_ports -filter { name =~ adcSync* }]

set_property -dict { PACKAGE_PIN M19 } [get_ports { DcoClk_0 }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ DcoClk* }]

set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[0] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[1] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[2] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[3] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[4] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[5] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[6] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[7] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[8] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[9] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[10] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[11] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[12] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[13] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]

#set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n

create_clock -period 10.000 -name DcoClk_0 -waveform {0.000 5.000} [get_ports DcoClk_0]
create_generated_clock -name adcClkIn_p_0 -source [get_pins design_1_i/ZmodADC1410_Controll_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports adcClkIn_p_0]

set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}]
set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}]
set_input_delay -clock [get_clocks DcoClk_0] -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}]
set_input_delay -clock [get_clocks DcoClk_0] -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}]

# Syzygy Port B
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[0] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19]
set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[1] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18]
set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[2] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6]
set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[3] }]; #IO_L10N_T1 Sch=syzygy_b_s[20]
set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[4] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16]
set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[5] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17]
set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[6] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7]
set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[8] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5]
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS18 } [get_ports { sDAC_Data_0[9] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5]
set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[10] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3]
set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[11] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3]
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[12] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1]
set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[13] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1]

set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Clkin_0 }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p
set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS18 } [get_ports { dADC_ClkIO_0 }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p

set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports { dADC_SDIO_0 }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4]
set_property DRIVE 4 [get_ports sDAC_SDIO_0]
set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS18 } [get_ports { dADC_CS_0 }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4]
set_property DRIVE 4 [get_ports sDAC_CS_0]
set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 } [get_ports { dADC_SCLK_0 }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2]
set_property DRIVE 4 [get_ports sDAC_SCLK_0]

set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS18 } [get_ports { dADC_SetFS1_0 }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0]
set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { dADC_SetFS2_0 }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0]
set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS18 } [get_ports { dADC_Reset_0 }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2]
set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS18 } [get_ports { dADC_EnOut_0 }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6]

create_generated_clock -name sDAC_Clkin_0 -source [get_pins design_1_i/ZmodAD1410_Controll_0/U0/InstDAC_ClkinODDR/C] -divide_by 1 [get_ports sDAC_Clkin_0]
create_generated_clock -name sDAC_ClkIO_0 -source [get_pins design_1_i/ZmodADC1410_Controll_0/U0/InstDAC_ClkIO_ODDR/C] -divide_by 1 [get_ports sDAC_ClkIO_0]

set_output_delay -clock [get_clocks sDAC_Clkin_0] -clock_fall -min -add_delay -0.100 [get_ports {dADC_Data_0[*]}]
set_output_delay -clock [get_clocks sDAC_Clkin_0] -clock_fall -max -add_delay 0.250 [get_ports {dADC_Data_0[*]}]
set_output_delay -clock [get_clocks sDAC_Clkin_0] -min -add_delay -0.100 [get_ports {dADC_Data_0[*]}]
set_output_delay -clock [get_clocks sDAC_Clkin_0] -max -add_delay 0.150 [get_ports {dADC _Data_0[*]}]

artvvb · July 12, 2023

Hey Xband,

Ports and clocks referenced in constraints need to match ports and clocks in your design. Presumably, you have two instances of the ADC controller instantiated, which both have their own ports connected to input/output ports. This means that, for example, I'd expect that you would need to be constraining two instances of each port - let's say for example "ZmodA_dADC_Data_0[0]" and "ZmodB_dADC_Data_0[0]" instead of a single "dADC_Data_0[0]" twice.

Also note that the ports for the DAC controller, which are constrained to the Zmod B pins, aren't 1:1 matches with the ADC controller's; the clocks go in different directions for one example.

Broadly, how I'd approach it would be to start by copying the Zmod A constraints, update all of the package_pin locations to match corresponding locations in Zmod port B, then update all of the names in get_ports, get_pins, and get_clocks calls to match the names used by the second controller in the hardware design.

For an overview of constraints, you might check out these blog posts. They're not 100% applicable, and this is a very complex design to be trying to modify when starting out, but they might help with some terminology.

Xilinx's UG903 covers everything in excruciating detail:

https://docs.xilinx.com/v/u/2019.1-English/ug903-vivado-using-constraints

Thanks,

Arthur

Xband · July 13, 2023

Thanks!

Xband · September 6, 2023

@artvvb,

Dug this constraint file out of github. The structure is different but looks like it might be for the Zmod scope setup. Is it ok to drop it in?

https://github.com/Digilent/vivado-hierarchies/blob/master/ZmodADC/constrs/ZmodADC.xdc

Ran synthesis after getting rid of "Circularbuffer" issues leftover from DAC project, this may have been the cause of some of the earlier errors. Synthesis was successful but seemed to still be looking at my old constraints file, disabled the file and am running again with the above constraints.

I don't think it worked. will go back and try to modify the .xdc file again.

attached runmelog from

C:\Users\Documents\GitHub\DualADC_1410_IP\DualADC_1410_IP.runs\impl_1

runme.log

Thanks,

JIm

Edited September 6, 2023 by Xband

Xband · September 6, 2023

What am I missing that none of my object names match?

artvvb · September 7, 2023

Please review your HDL wrapper module, and confirm that all port names in XDCs match names in the wrapper. The issue with the github source that you linked is that it is intended to be used with a script that reproduces part of a block design, which also finds and replaces all of the "nameHier" text in the XDC. It then has the correct names of ports, since it creates the ports in a known way, as long as ports aren't manually renamed later.

Thanks,

Arthur

Xband · September 7, 2023

@artvvb can I modify the design wrapper along with the constraint file? Since there are 2 zmod 1410 modules the design wrapper has duplicate names for many of the variables.

artvvb · September 7, 2023

Editing the wrapper is possible. Also, any changes to the block diagram should cause the wrapper to update, though it can be finicky. That said, duplicate names likely mean that things are connected to the same net - this is hardware design, all signal names represent some wire somewhere in the FPGA - if both Scope 1410 controller IPs are connected to the same input port, the design won't work correctly, since the inputs need to be connected to the actual physical Zmods.

Xband · September 7, 2023

@artvvb I'm not seeing a difference, is it obvious to the trained eye?

I've also deleted earlier design wrappers and regenerated everything. Still having the same problem.

Pin M20 is duplicated in the constraint file but I wouldn't think that is the main problem.

design

--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Thu Sep 7 10:40:10 2023
--Host : JIMT16 running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DcoClk_0 : in STD_LOGIC;
DcoClk_1 : in STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
adcClkIn_n_0 : out STD_LOGIC;
adcClkIn_n_1 : out STD_LOGIC;
adcClkIn_p_0 : out STD_LOGIC;
adcClkIn_p_1 : out STD_LOGIC;
adcSync_0 : out STD_LOGIC;
adcSync_1 : out STD_LOGIC;
btn_2bits_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
dADC_Data_0 : in STD_LOGIC_VECTOR ( 13 downto 0 );
dADC_Data_1 : in STD_LOGIC_VECTOR ( 13 downto 0 );
rgbled_6bits_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
sADC_CS_0 : out STD_LOGIC;
sADC_CS_1 : out STD_LOGIC;
sADC_SDIO_0 : inout STD_LOGIC;
sADC_SDIO_1 : inout STD_LOGIC;
sADC_Sclk_0 : out STD_LOGIC;
sADC_Sclk_1 : out STD_LOGIC;
sCh1CouplingH_0 : out STD_LOGIC;
sCh1CouplingH_1 : out STD_LOGIC;
sCh1CouplingL_0 : out STD_LOGIC;
sCh1CouplingL_1 : out STD_LOGIC;
sCh1GainH_0 : out STD_LOGIC;
sCh1GainH_1 : out STD_LOGIC;
sCh1GainL_0 : out STD_LOGIC;
sCh1GainL_1 : out STD_LOGIC;
sCh2CouplingH_0 : out STD_LOGIC;
sCh2CouplingH_1 : out STD_LOGIC;
sCh2CouplingL_0 : out STD_LOGIC;
sCh2CouplingL_1 : out STD_LOGIC;
sCh2GainH_0 : out STD_LOGIC;
sCh2GainH_1 : out STD_LOGIC;
sCh2GainL_0 : out STD_LOGIC;
sCh2GainL_1 : out STD_LOGIC;
sRelayComH_0 : out STD_LOGIC;
sRelayComH_1 : out STD_LOGIC;
sRelayComL_0 : out STD_LOGIC;
sRelayComL_1 : out STD_LOGIC;
sys_clock : in STD_LOGIC
);
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
btn_2bits_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
rgbled_6bits_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
sys_clock : in STD_LOGIC;
DcoClk_0 : in STD_LOGIC;
dADC_Data_0 : in STD_LOGIC_VECTOR ( 13 downto 0 );
DcoClk_1 : in STD_LOGIC;
dADC_Data_1 : in STD_LOGIC_VECTOR ( 13 downto 0 );
adcClkIn_p_0 : out STD_LOGIC;
adcClkIn_n_0 : out STD_LOGIC;
adcSync_0 : out STD_LOGIC;
sADC_SDIO_0 : inout STD_LOGIC;
sADC_CS_0 : out STD_LOGIC;
sADC_Sclk_0 : out STD_LOGIC;
sCh1CouplingH_0 : out STD_LOGIC;
sCh1CouplingL_0 : out STD_LOGIC;
sCh2CouplingH_0 : out STD_LOGIC;
sCh2CouplingL_0 : out STD_LOGIC;
sCh1GainH_0 : out STD_LOGIC;
sCh1GainL_0 : out STD_LOGIC;
sCh2GainH_0 : out STD_LOGIC;
sCh2GainL_0 : out STD_LOGIC;
sRelayComH_0 : out STD_LOGIC;
sRelayComL_0 : out STD_LOGIC;
adcClkIn_p_1 : out STD_LOGIC;
adcClkIn_n_1 : out STD_LOGIC;
adcSync_1 : out STD_LOGIC;
sADC_SDIO_1 : inout STD_LOGIC;
sADC_CS_1 : out STD_LOGIC;
sADC_Sclk_1 : out STD_LOGIC;
sCh1CouplingH_1 : out STD_LOGIC;
sCh1CouplingL_1 : out STD_LOGIC;
sCh2CouplingH_1 : out STD_LOGIC;
sCh2CouplingL_1 : out STD_LOGIC;
sCh1GainH_1 : out STD_LOGIC;
sCh1GainL_1 : out STD_LOGIC;
sCh2GainH_1 : out STD_LOGIC;
sCh2GainL_1 : out STD_LOGIC;
sRelayComH_1 : out STD_LOGIC;
sRelayComL_1 : out STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
DcoClk_0 => DcoClk_0,
DcoClk_1 => DcoClk_1,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
adcClkIn_n_0 => adcClkIn_n_0,
adcClkIn_n_1 => adcClkIn_n_1,
adcClkIn_p_0 => adcClkIn_p_0,
adcClkIn_p_1 => adcClkIn_p_1,
adcSync_0 => adcSync_0,
adcSync_1 => adcSync_1,
btn_2bits_tri_i(1 downto 0) => btn_2bits_tri_i(1 downto 0),
dADC_Data_0(13 downto 0) => dADC_Data_0(13 downto 0),
dADC_Data_1(13 downto 0) => dADC_Data_1(13 downto 0),
rgbled_6bits_tri_o(5 downto 0) => rgbled_6bits_tri_o(5 downto 0),
sADC_CS_0 => sADC_CS_0,
sADC_CS_1 => sADC_CS_1,
sADC_SDIO_0 => sADC_SDIO_0,
sADC_SDIO_1 => sADC_SDIO_1,
sADC_Sclk_0 => sADC_Sclk_0,
sADC_Sclk_1 => sADC_Sclk_1,
sCh1CouplingH_0 => sCh1CouplingH_0,
sCh1CouplingH_1 => sCh1CouplingH_1,
sCh1CouplingL_0 => sCh1CouplingL_0,
sCh1CouplingL_1 => sCh1CouplingL_1,
sCh1GainH_0 => sCh1GainH_0,
sCh1GainH_1 => sCh1GainH_1,
sCh1GainL_0 => sCh1GainL_0,
sCh1GainL_1 => sCh1GainL_1,
sCh2CouplingH_0 => sCh2CouplingH_0,
sCh2CouplingH_1 => sCh2CouplingH_1,
sCh2CouplingL_0 => sCh2CouplingL_0,
sCh2CouplingL_1 => sCh2CouplingL_1,
sCh2GainH_0 => sCh2GainH_0,
sCh2GainH_1 => sCh2GainH_1,
sCh2GainL_0 => sCh2GainL_0,
sCh2GainL_1 => sCh2GainL_1,
sRelayComH_0 => sRelayComH_0,
sRelayComH_1 => sRelayComH_1,
sRelayComL_0 => sRelayComL_0,
sRelayComL_1 => sRelayComL_1,
sys_clock => sys_clock
);
end STRUCTURE;

constraints.xdc

# 125MHz Clock from Ethernet PHY
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L12P_T1_MRCC Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }];