Search the Community

Showing results for tags 'vivado'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







  1. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  2. Hi there! I'm an electrical engineering student and my group has been thrown in cold water: We have to do an SPI Project where we connect a PMOD-Mic3 to our Basys3 Board and measure the frequencies of sounds by giving the Mic signal out to the onboard LEDs. A lot of LEDs have to light up when the frequency is high (over 500 Hz) and less when the frequency gets lower. [We have to create a Vivado VHDL Project.] We have huge problems understanding the core of the exercise. So far, after hours of research, we were not succesful with anything but especially: Establishing SPI-Communication (Master-Slave) Creating working shift-registers Our question is: has anyone done anything like that and can provide us with tipps/tricks or even a working examplary code? We value copyright and would never copy your work, we just need an idea as we have never dealt with FPGAs, VHDL or SPI before. We would appreciate every answer, thank you all a lot in advance! Your ElectricalEngStudent :)
  3. Just starting with FPGA's and using the Zedboard. I have a simple program that uses switches to turn on/off the leds. When I power cycle the board the program seems to be erased and I have to reprogram the board. How can I make this persistent (I am using Vivado)?
  4. Hi everyone, I want to send some sobel edge data I get from Vivado HLS application to Vivado SDK application. What is the best way for to carry with uart protocol or ethernet protocol.
  5. Hi, I have recently bought the Genesys Zu 5EV and i have some problems with the tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" i have tried to reproduce all point step by step but i have some errors and i am wondering if there is some problem on the guide or with the versions. Here are all steps i have followed and the problems/errors i get: Vivado part In the step "Add a Zynq UltraScale+ Processor to a Block Design" In the part that says "The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard." When they suggest to add a second clock, looks like it is not necessary, if I add it then I have an error afterwards about where to connect this pin. To solve this issue I have removed this clock (i assume is not necessary to have a second clock here). Tehrefore i have also avoid the part of "add a Concat IP to your block design, and manually connect it to the pl_ps_irq0 port." In step "Add GPIO Peripherals to a Block Design" part of AXI_GPIO_BUTTONS First i add the xdc file Genesys-ZU-5EV-D-Master.xdc for the contraints In the guide it says "_the button interface to “btn_tri_io[#]”, where # is a decimal number, counting up from zero. When finished, save the file_.". However the button on the Genesys-ZU-5EV-D-Master.xdc starts on 2 until 6 I have re-named the file as suggested in the guide However the guide says "In particular, the width of the GPIO interface must match the number of buttons available on the board." and i f i am not wrong in the genesys zu board there are 7 buttons not 5 (BTN0, BTN1, BTNL, BTNR, BTNU, BTND,BTNC) but the xdc file only defines 5, is this correct? In step Edit the Address Map Here the values are different that the ones of the guide, but i have checked that there is no Assigning an segment to address 0 to avoid errors as explained in the guide. is this correct? In step "Validate a Block Design" it shows an error in the pin saxihpc0_fdp_aclk Following the figures of the guide (even if they are not the same for the zynq ultrascate), I have connected the pin that produce the error (_saxishpc0_fdp_aclk_) to the pin _pl_clk0_ (clock) pin. Sfter that the validation is ok, is this correct? The validation now is ok, but it shows the following warning messages Vitis part In the "Create a New Application Project" When i have to select the Aplication project details. Which Processor should i use? In the guide the picture is different. Is it correct to use the first one _psu_cortexa53_0_ ? As suggested in the guide " Change the BTN_MASK and LED_MASK macros so that they contain a number of '1's equal to the number of buttons and leds connected to the GPIO peripherals in the hardware design." Here i assume is 5 for buttons and 4 for leds as i did it in the vivado part is this correct? how do i know the buttons and leds connected to the GPIO peripherals in the hardware design ? In the step "Launch a Vitis Baremetal Software Application" When i try to make _Run as → 1 Launch on Hardware (Single Application Debug)._ It pops up an error window. If i run with the option " Launch on emulator" looks like is working, but i do not knw how to test the buttons and leds there. Many thanks, log_build_vivado_project.txt
  6. Hello All, I am Mahdi and a new comer to this forum. I am going to order a Genesys 2 Kintex-7 FPGA Development Board and before that I have couple of questions. 1) The board coming with the Node-Lock/floating License or Voucher? if so for how many person and for how long? 2) With purchasing the board, Can I simulate/synthesis and implement my design via Vivado on the Gensys 2 Board? If not what I should do? Purchase new product or download and install something will be good? 3) What does it mean when the support expires? Thanks in advance for help Best,
  7. Hi, I am new to FPGA and starting with "Hello word" project on Cora Z7 (XCZ010-1CLG400C). I am following the "Getting Started" Hello world project from digilent available on the following link; However I get this following error that is not pointing out the source of the error. [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Please see attached snapshot of the project Diagram and the errors reported. Thanks
  8. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  9. Hey Everyone, I am designing a project in which i used a custom soft core and LMB Bus, LMB Controller followed by Dual port BRAM for Data and instruction read write operations , The custom soft core is WORD ALIGNED. The problem is that during the post implementation functional simulation the 32 bit Word aligned address that i am sending to the bram memory, the unused bits in the address port of BRAM is considered as 'Z' and hence when i dump the code in the FPGA the address is different(for eg. if i give address as 8000, 8004 its considering it as 2000,2001). The address port of FPGA is observed using ILA core. Hence i am not able to read the memory content form correct location. i found a clue to solving this one in LMB controller which is that the LMB controller masks the unused bits to 'Z' in the address for access to LMB. But if i override the masking as manual and setting it to FFFFFFFF int IP customization, the design is still giving 'Z' for the unused address bits. how can i overcome this problem? Below are the screenshots for the reference Thanks
  10. Hi, I am having a problem in programming my FPGA. There was no problem in synthesis, implementation and generating bitstream. However, I got these errors: "[Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. [Labtools 27-3165] End of startup status: LOW". After generating .bin file instead of .bit file, I got rid of the first error [Labtools 27-3303]. However, I stil cannot program the FPGA because of the second error [Labtools 27-3165]. I have tried different versions of vivado, different BASYS3 FPGAs, different computers, and cables, but I can't solve it. I don't get these errors in my other codes but only in designs using VGA port of the FPGA.
  11. sciaomi


  12. I am frustrated with Vivado 2022.1 and was going to install the update to Vivado 2022.2 but that is 50GB download, and may not resolve the issues I'm having. Are there alternatives that allow the development in Verilog, and can create the bitstream to program a Zybo Z7-20?
  13. I hate upgrading to new Vivado releases unless there's a compelling reason to do so. Well, Vivado ML, AKA Vivado 2021.2, is one of those reasons. The bad news is that it's a 64 GB install ( not including Petalinux ). The good news is that the unified installer actually installs everything, including Petalinux. More importantly, this release supports many more ZYNQ UltraScale+ devices, including the ZCU106 ZU7EV, for free. Of course there's a price to pay. One is that installing the Digilent board files into Vivado has to be changed. Now there's the xHUB XilinxBoardStore format. Has anyone looked into resolving this?
  14. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  15. Hello, everyone. I am having difficult finding a guide or solution to this problem. I would like to simply connect a switch (G15 on the Z720) to my custom IP that should toggle a Clean or Distortion signal. For some reason I am unable to insert a link to the Block Diagram: In the diagram you can see that I had originally just made CTRL external and added it to the constraints file for pin G15, but this did not work. I'm think that I need to instantiate GPIO in Vitis to use this method, but so far I haven't had any luck. My next thought was to use the AXI_GPIO block and somehow tie it to both sws_4bits and the CTRL port on Serialeffects, but that is what I cannot figure out how to do. Does anyone have a resource for learning how to do this? I'm open to any suggestions, as I would eventually like to use the 4 switches on the board to control different audio effects, such as chorus, echo, etc.
  16. Dear all In vivado design flow in setup debug step I am seeing multiple netlist for only three bit register "state". How can i identify my original signal to debug my design thank you
  17. As is described before, I have been developing PmodBT2 using microblaze. After I generate bit file, I lanuch SDK, many errors occur as follows. And vivado version is 2018.3. Is there anyone to give me some guidance? I spent several hours, but still fail. Wish your reply. Thanks a lot.
  18. Hello, I am working with ZedBoard. I have created a custom IP using Vivado for my project. I have tested the working of my custom IP by setting the registers using "Xil_Out32 function (Xilinx SDK baremetal application)" . I have also stored output data of my custom IP to text file on the SD card (using xilffs). Now my objective is to create a petalinux project and implement similar functions(how I have used in baremetal). I dont know how to use Xil_out and xilffs library functions in petalinux. According to my understanding these are specifiaclly used in baremetal application. (in Xilinx SDK). It would be great for me if someone guide me for creating petalinux project application my project. Thanks and regards
  19. I need to use the JTAG header to program the Zedboard, since the MicroUSB connector is physically damaged. I cannot find any documentation or forums about how to use the JTAG connector for programming the FPGA, so I am going to ask for your help. I have a basic design in Vivado for making switch 0 toggle led 0. The bitstream is ready to be sent to the FPGA. However, when I try to connect to the hardware, by clicking "Open target", it is unable to connect. When I try to manually connect: I am using Xilinx Platform Cable USB adapter for connecting the JTAG to the computer's USB input: I have the driver installed, and it appears in my list of devices when plugged in, and disappears if I unplug it, and is up-to-date: I suspect the jumpers may not be configured properly? But again I cannot find clear documentation on how to set this up. This is how mine is set up: Here is some information about my computer: I am using Vivado 2016.1, since that is used in a lot of the tutorials. I think the Diligent tutorial uses 2016.2. It also comes with the Zedboard board file, although I downloaded the one made by Diligent as instructed in the tutorial. I hope I have provided enough information. I appreciate any help!
  20. so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF] > pclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y43 and pclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7 error 2 : [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. error 3 : [Common 17-69] Command failed: Placer could not place all instances here is a link where you should find everything you need if you you want to take a look :
  21. Hi all, this is my first time posting here because I really need the 2019.4 version of the Xilinx Vivado SDK. I deleted it when I updated to the 2020.2 version today forgetting everything I have would be uncomeatable. I went to redownload the 2019.4 version but only the 2019.1 version was available on the website, this also didn't work. ( If anybody has it installed or knows where I could get it I would be grateful. I was also wondering if anybody has a contact at Xilinx that may be able to provide it. Thank you everybody I really need the help
  22. Hi im getting these warnings while i try to validate design in Vivado while executing hello world program which makes use of Zynq 7000 boards. i kindly request you to give a siolution for these warnings [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.
  23. Hello All, I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples. I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting. i came across things like FSBL (First Stage Boot Loader), along with the bit stream from Vivado project, then i wanted to avoid the SDK by using only Vivado and exporting the hardware which requires other stuff like a block design which require other stuff like IP blocks and connecting things together that i have no idea about. It's an interconnected mess for me. I would really appreciate someone who came across that and describe the process in simple details. Sorry if i lack some basics, my aim at the end is to read a PWM signal (frequency and duty cycle) and produce them again by changing them e.g. input is 5 kHz and 90% and output from FPGA is 5 kHz and 60%, the FPGA should act as a duty cycle limiter. My chip is: Zybo (xc7z010clg400-1) (picture attached) Software: Vivado 2018.1 Best regards, MJ
  24. My Basys3 board is not recognized in Vivado. I installed Vivido v2020.2 with little effort (although it took well over an hour). When I connect the USB cable and turn the power on nothing happens inside of Vivido. My board is jumpered for JTAG using JP1 (center pins). If I view the hardware manager it shows "unconnected No hardware target open". Clicking Open target than auto-connect shows no change. Only localhost (0) connected is listed. In Windows10 device manager, I do see 2 USB entries labeled "Digilent USB Device" with a value of, Dual RS232-HS (interface 0) and Dual RS232-HS (interface 1). I have power cycled my computer but no change. I can successfully copy the Project.BIT file to a USB drive and load the board that way after changing the jump. What do I try next to establish JTAG connection?
  25. Good Afternoon Sir/Madam, I am trying to display the internal temperature of my device on a four 7-segments anodes hexadecimally. In my attached archive, I have already instantiated the XADC. After going over the user manual of 7 Series FPGAs and Zynq-7000 SoC XADC, Here is what I already know: I am aware that the measured temperature value is in address 00h. I am aware that channels 4 to 0 need to be all zeros to measure the on chip temperature. I am aware that the first 64 access locations (DADDR[6:0] = 00h to 3Fh) of DRP are read only which contain the ADC measurement data. Here is what I don't understand: -Why am I getting zeros from the output of Dynamic Reconfiguration Port (DRP)? For your information, I am programming in VHDL on Vivado 2020.1. Kind regards, ElectronicEngineer