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Found 16 results

  1. Hi there, I am quite new to FPGA and would like first to apologize if my question is *stupid* :-) I have read already quite a lot and I am kind of stuck. Any help appreciated ? Hardware Card: Nexys Video Vivado 2016.4 What I would like to do I have an external TTL signal (3.3 V, 1 kHz) connected to the Pmod A, ja[0] pin (and the ground to GNB) . As a test, I would like to read this signal, fill a FIFO and then read the FIFO buffer when the buffer is full. I do not mind to lose data; I just want to see (on the computer) some raw data once in a while. ISSUES From the SDK terminal, I receive weird data like "²’ÒŠRj$ª²šÒŠRj$ª²¢". My top module `timescale 1ns / 1ps module oscillo(clk, uart_rx_out, TTL_in,sw); input clk; input sw; input [0:0] TTL_in; // These are input data output uart_rx_out; reg [0:0] TTL_in_reg; always @(posedge clk) TTL_in_reg <= TTL_in; wire [0:0] q_fifo; // These are output data fifo_generator_0 myFifo ( .clk(clk), // input wire clk .din(TTL_in_reg), // input wire [0 : 0] din .wr_en(wrreq), // input wire wr_en .rd_en(rdempty), // input wire rd_en .dout(q_fifo), // output wire [0 : 0] dout .full(wrfull), // output wire full .empty(wrempty) // output wire empty ); // The flash ADC side starts filling the fifo only when it is completely empty, // and stops when it is full, and then waits until it is completely empty again reg fillfifo; always @(posedge clk) if(~fillfifo) fillfifo <= wrempty; // start when empty else fillfifo <= ~wrfull; // stop when full assign wrreq = fillfifo; assign rdempty = ~ fillfifo; microblaze_mcs_0 myMCS ( .Clk(clk), // input wire Clk .Reset(sw), // input wire Reset .GPI1_Interrupt(GPI1_Interrupt), // output wire GPI1_Interrupt .INTC_IRQ(INTC_IRQ), // output wire INTC_IRQ .UART_txd(uart_rx_out), // output wire UART_txd .GPIO1_tri_i(fillfifo), // input wire [0 : 0] GPIO1_tri_i .GPIO2_tri_i(q_fifo) // input wire [0 : 0] GPIO2_tri_i ); endmodule My xdc file ## FPGA Configuration I/O Options set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { TTL_in }] ## Board Clock: 100 MHz set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; create_clock -add -name clk_100m -period 10.00 [get_ports clk] ## Reset Switch set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw}]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }] My helloword.c for the sdk #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xparameters.h" // add #include "xiomodule.h" // add volatile char int_flag = 0; // millisecond counter variable //function which is called by the GPI interrupt when one of its bits goes hi void MyInterruptFlagSet( void* ref) { int_flag = 1; // when it receives interrupt, set c } int main() { init_platform(); u32 data; u16 my_secs = 0; XIOModule gpi; //print("Setting up GPI\n\r"); data = XIOModule_Initialize(&gpi, XPAR_IOMODULE_0_DEVICE_ID); data = XIOModule_Start(&gpi); //setting up interrupt handlers and enables them microblaze_register_handler(XIOModule_DeviceInterruptHandler, XPAR_IOMODULE_0_DEVICE_ID); // register the interrupt handler // Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. XIOModule_Connect(&gpi, XIN_IOMODULE_GPI_1_INTERRUPT_INTR, MyInterruptFlagSet, NULL); // register timerTick() as our interrupt handler XIOModule_Enable(&gpi, XIN_IOMODULE_GPI_1_INTERRUPT_INTR); // enable the interrupt microblaze_enable_interrupts(); // enable global interrupts while (1) { while(int_flag == 0 ) //wait till interrupt flag goes high ; data = XIOModule_DiscreteRead(&gpi, 2); // read counts (channel 2) xil_printf("%d: %d\n\r",my_secs, data); my_secs++; int_flag = 0; //clear flag } cleanup_platform(); return 0; }
  2. I am trying to interface PMOD DA4 with atlys FPGA but nothing is coming at output. help me to rectify what wrong with code. module spi_master_v1( input sys_clk, input rst, output reg cs, output reg MOSI, output reg sclk, // input [31:0] in_data, output reg done ); // Internal registers reg [10:0] count; reg [31:0] temp_data; reg [5:0] bit_count; reg [11:0] count2; // state declearation reg [1:0] state; parameter idle = 2'b00; parameter data_tx = 2'b01; parameter finish = 2'b10; //initialize all register initial begin cs = 1; MOSI = 0; sclk = 0; done = 0; count = 0; temp_data =32'b00000000000000000000000000000000; bit_count = 0; state = 0; count2 = 0; end // clock dividwer always @(posedge sys_clk) begin if (count == 4) begin sclk <= ~sclk; count <= 11'b00000000000; end else begin count = count +1; end end // functional design always @(posedge sclk) begin case (state) idle : begin done = 1'b0; cs = 1'b1; state = data_tx; temp_data[7:0] = 8'b00000000; temp_data[19:8] = count2; temp_data[31:20] = 12'b100000001111; MOSI = 0; count2 = count2 + 1; end data_tx: begin cs = 1'b0; MOSI = temp_data[31-bit_count]; if (bit_count == 32) begin state = finish; bit_count = 0; done = 1'b1; MOSI = 0; end else begin bit_count = bit_count + 1; end end finish: begin cs = 1'b1; state = idle; MOSI = 0; end endcase end endmodule
  3. After executing the attached code, my EPWave does not give me the required output clock signals as it reaches logic level '1' in the beginning and stays the same throughout the waveform. I would highly appreciate it if someone could help me out by giving a prompt response. Please note: The above Verilog code is executed in a Cadence Xcelium 20.09 simulator. CODE AND TESTBENCH.docx
  4. I am in the proposal process that utilizes the Eclypse Z7 along with the Zmod ADC 1410. We are hoping to utilize vetted code to configure the ADC and accept the sample data. We need to do some processing and interfacing to external components so we cannot use the provided bit file. I have looked over GitHub repository (https://github.com/Digilent/Eclypse-Z7-HW) and couldn’t find any VHDL or Verilog files?
  5. Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mhz with 2.5 to get 40Mhz clk frequency. I tried many combinations of DCM properties (like setting external clkin and internal, changing feedback properties etc.) but was not successful. I am uploading the whole code directory archived in a Winrar, so you can also maybe replicate the issue. Any help is appreciated! Thanks in advance. lab9v360hz.rar
  6. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <= 0; sclk <= 0; end else begin count <= count + 1; if(count == 1) begin sclk <= ~sclk; count <= 0; end end end endmodule __ `timescale 1ns / 1ps module spi0( input clock, input reset, input send, output sclk0, output reg cs, output reg ldac, output reg din ); reg[15:0] data [3:0]; reg[15:0] count; reg [1:0] sel; sclk sclk_inst ( .clock(clock), .reset(reset), .sclk(sclk0) ); initial begin data[0] = 16'b0101111000010101; data[1] = 16'b1000011111100001; count = 16'd16; cs = 1; sel = 0; end always @ (negedge sclk0 & send == 1)begin if (send == 1)begin if ( count > 0)begin cs = 0; ldac = 0; end if (count == 0)begin cs = 1; ldac = 1; count = 16'd16; end din = data[sel][count-1]; count = count - 1; end end endmodule __ `timescale 1ns / 1ps module spi0_testbench(); reg clock = 0; reg reset = 0; reg send = 0; reg [50:0]counter = 0; reg [16:0] i; wire sclk0; wire cs; wire ldac; wire din; wire[15:0] count; spi0 UUT(clock, reset, send, sclk0, cs, ldac, din); always @ (*)begin #10 if (i >= 127 & i < 129)begin send = 0; end if (i < 127 | i >= 129) begin send = 1; end if (i < 127)begin end end initial begin for (i = 0; i < 1000; i = i + 1)begin clock = ~clock; counter = counter + 1; #1; end end endmodule Green: SCLK Yellow: DIN Blue: CS Pink: LDAC
  7. I have developed a library component with the usual clock input. The component's logic needs to know at what frequency its clock is running at, which of course is unknown at component creation time. Is there a way, in Verilog, to extract a port or a net's frequency at design synthesis time once the block has been connected to an actual clock? To express the frequency as a wire?
  8. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf
  9. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiBl_HfzovoAhVKY5oKHfNPBt0QFjABegQIAhAB&url=http%3A%2F%2Fwww.latticesemi.com%2Fview_document%3Fdocument_id%3D28236&usg=AOvVaw3HSzLdNneCLsy5wEoUnUOx) I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf
  10. i enter 5V in FFT so maybe the result are just on impulse signal. but actuality my result have unexpected -'128 signals' (263~390 cnt ) why does -128 apear. and how to disapear unexpected value (-128)
  11. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance
  12. Ahmed Alfadhel

    Verilog

    Hi , I want to learn Verilog . What you suggest for me to start with ? Any recommended books , websites or online courses? Thanks
  13. Hi @D@n Thanks for your replies to my questions . They are very helpful . I just want to know does it possible to download Verilator on Windows? If not possible , what are the available options for me to download a Verilog Simulator on Windows? Thanks.
  14. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  15. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?
  16. I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, output reg HSync1, output reg VSync1 ); VHDL: component testoverlay_0 is port ( rst_n: in STD_LOGIC; clk: in STD_LOGIC; RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 ); HSync1: out STD_LOGIC; VSync1: out STD_LOGIC ); end component testoverlay_0; test_overlay: component testoverlay_0 port map ( rst_n => reset_1, clk => sys_clk_i_1, RGBOut(23 downto 0) => v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0), HSync1 => v_axi4s_vid_out_0_vid_io_out_HSYNC_1, VSync1 => v_axi4s_vid_out_0_vid_io_out_VSYNC_1 );
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