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Found 11 results

  1. Hi, I have recently bought the Genesys Zu 5EV and i have some problems with the tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi i have tried to reproduce all point step by step but i have some errors and i am wondering if there is some problem on the guide or with the versions. Here are all steps i have followed and the problems/errors i get: Vivado part In the step "Add a Zynq UltraScale+ Processor to a Block Design" In the part that says "The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard." When they suggest to add a second clock, looks like it is not necessary, if I add it then I have an error afterwards about where to connect this pin. To solve this issue I have removed this clock (i assume is not necessary to have a second clock here). Tehrefore i have also avoid the part of "add a Concat IP to your block design, and manually connect it to the pl_ps_irq0 port." In step "Add GPIO Peripherals to a Block Design" part of AXI_GPIO_BUTTONS First i add the xdc file Genesys-ZU-5EV-D-Master.xdc for the contraints In the guide it says "_the button interface to “btn_tri_io[#]”, where # is a decimal number, counting up from zero. When finished, save the file_.". However the button on the Genesys-ZU-5EV-D-Master.xdc starts on 2 until 6 I have re-named the file as suggested in the guide However the guide says "In particular, the width of the GPIO interface must match the number of buttons available on the board." and i f i am not wrong in the genesys zu board there are 7 buttons not 5 (BTN0, BTN1, BTNL, BTNR, BTNU, BTND,BTNC) but the xdc file only defines 5, is this correct? In step Edit the Address Map Here the values are different that the ones of the guide, but i have checked that there is no Assigning an segment to address 0 to avoid errors as explained in the guide. is this correct? In step "Validate a Block Design" it shows an error in the pin saxihpc0_fdp_aclk Following the figures of the guide (even if they are not the same for the zynq ultrascate), I have connected the pin that produce the error (_saxishpc0_fdp_aclk_) to the pin _pl_clk0_ (clock) pin. Sfter that the validation is ok, is this correct? The validation now is ok, but it shows the following warning messages Vitis part In the "Create a New Application Project" When i have to select the Aplication project details. Which Processor should i use? In the guide the picture is different. Is it correct to use the first one _psu_cortexa53_0_ ? As suggested in the guide " Change the BTN_MASK and LED_MASK macros so that they contain a number of '1's equal to the number of buttons and leds connected to the GPIO peripherals in the hardware design." Here i assume is 5 for buttons and 4 for leds as i did it in the vivado part is this correct? how do i know the buttons and leds connected to the GPIO peripherals in the hardware design ? In the step "Launch a Vitis Baremetal Software Application" When i try to make _Run as → 1 Launch on Hardware (Single Application Debug)._ It pops up an error window. If i run with the option " Launch on emulator" looks like is working, but i do not knw how to test the buttons and leds there. Many thanks, log_build_vivado_project.txt
  2. I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. https://forum.digilentinc.com/topic/8943-pmod-as-input-and-output-gpio/ #Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }]; set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je_pin4_io }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je_pin7_io }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je_pin8_io }]; set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je_pin9_io }]; set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je_pin10_io }]; I am able to control the GPIO pins of port JF on the Zybo Z720 using the following code, how do I edit this so that I am able to turn on/off LEDs using the Pmod port JE instead. #include "xil_cache.h" #include "xparameters.h" #include "stdio.h" #include "xparameters.h" #include "xuartps.h" #include "xtime_l.h" #include "xgpiops.h" #include "sleep.h" #include "xil_io.h" #include "xil_types.h" #include "xil_printf.h" #include "sleep.h" #include "stdlib.h" #include "string.h" #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) #define TIMER_FREQ_HZ 100000000 #define MAX_WIDTH 320 #define MAX_HEIGHT 240 #define MAX_BUTTON 16 #ifdef __MICROBLAZE__ #define HOST_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_BASEADDR #define HostUart XUartLite #define HostUart_Config XUartLite_Config #define HostUart_CfgInitialize XUartLite_CfgInitialize #define HostUart_LookupConfig XUartLite_LookupConfig #define HostUart_Recv XUartLite_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->RegBaseAddr) #include "xuartlite.h" #include "xil_cache.h" #else #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #include "xuartps.h" #endif #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define BLOCK_SIZE 40 void startup(); XGpioPs_Config *ConfigPtr; XGpioPs output; int main() { startup(); while(1) { XGpioPs_WritePin(&output, 13, 1); //led on (pin 1,2,3,4) XGpioPs_WritePin(&output, 10, 1); XGpioPs_WritePin(&output, 11, 1); XGpioPs_WritePin(&output, 12, 1); } void startup(){ //initialize pins for JF ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID); XGpioPs_CfgInitialize(&output, ConfigPtr, ConfigPtr->BaseAddr); XGpioPs_SetDirectionPin(&output, 13, 1); XGpioPs_SetOutputEnablePin(&output, 13,1); //pin1 JF1 XGpioPs_SetDirectionPin(&output, 10, 1); XGpioPs_SetOutputEnablePin(&output, 10,1); //pin2 JF2 XGpioPs_SetDirectionPin(&output, 11, 1); XGpioPs_SetOutputEnablePin(&output, 11,1); //pin3 JF3 XGpioPs_SetDirectionPin(&output, 12, 1); XGpioPs_SetOutputEnablePin(&output, 12,1); //pin4 JF4 }
  3. k-k

    Beginner needs help

    Hello, I am an beginner and use a Zybo Z20 Board Vivado and Vitis. I tryed the Tutorial: Getting Started with Vivado and Vitis for Baremetal Software Projects - Digilent Reference (it works) Now i tryed to add a RTL-Block (VHDL) and connect it with the axi-gpio. Then i want to manipulate it using vitis and a c-code, a LED should shine. But it doesn't work. Is there a tutorial how to connect PL and PS? Can someone help me? Thanks
  4. Hello, everyone. I am having difficult finding a guide or solution to this problem. I would like to simply connect a switch (G15 on the Z720) to my custom IP that should toggle a Clean or Distortion signal. For some reason I am unable to insert a link to the Block Diagram: https://imgur.com/a/D3uOchd In the diagram you can see that I had originally just made CTRL external and added it to the constraints file for pin G15, but this did not work. I'm think that I need to instantiate GPIO in Vitis to use this method, but so far I haven't had any luck. My next thought was to use the AXI_GPIO block and somehow tie it to both sws_4bits and the CTRL port on Serialeffects, but that is what I cannot figure out how to do. Does anyone have a resource for learning how to do this? I'm open to any suggestions, as I would eventually like to use the 4 switches on the board to control different audio effects, such as chorus, echo, etc.
  5. Just got myself a zedboard. says "copyright 2020" on the silkscreen so its fairly new. I'm stepping through the instructions here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1.0 (64-bit) because that seems to be the recommended version of tools for that tutorial. I tried a later version and a lot of the screenshots were completely different. When I get into vitis, I select the system project in the Assistant pane, and click the Build button (hammer). I get the following under the "Problems" tab: Description Resource Path Location Type fatal error: xgpio.h: No such file or directory main.c /project_1_app/src line 3 C/C++ Problem make: *** [makefile:38: package] Error 1 Debug /project_1_app_system C/C++ Problem When I look at the Vitis.log tab, I see the following, withi the zed.xsa error at the bottom: 12:45:48 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 12:45:48 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 12:45:48 INFO : Launching XSCT server: xsct.bat -n -interactive D:\workspace\temp_xsdb_launch_script.tcl 12:45:48 INFO : XSCT server has started successfully. 12:45:48 INFO : plnx-install-location is set to '' 12:45:48 INFO : Successfully done setting XSCT server connection channel 12:45:48 INFO : Successfully done setting workspace for the tool. 12:45:48 INFO : Platform repository initialization has completed. 12:45:48 INFO : Registering command handlers for Vitis TCF services 12:45:48 INFO : Successfully done query RDI_DATADIR 12:45:57 INFO : Checking for BSP changes to sync application flags for project 'project_1_app'... 12:46:03 ERROR : (XSDB Server)ERROR: [Hsi 55-1571] The design file D:/workspace/project_1_wrapper/export/project_1_wrapper/hw/zed.xsa is already opened at which point, the Vitis.log stops there. I've seen the "fatal error: xgpio.h: No such file or directory" on other posts this forum and elsewhere, but I have not seen a definitive answer to how to fix it. The only specific "try this" thing I've seen is try refreshing and try going back to vivado and rerun synthesis, implementation, and bitstream. Neither fixed the problem for me. I followed these instructions to download board files: https://reference.digilentinc.com/programmable-logic/guides/installation I copied the "new/board files" because instructions say that is for versions later than 2014.4 And when I google for "zed.xsa is already opened", I don't find it anywhere. any help would be appreciated
  6. Hi, Where can I find a tutorial to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? I've searched everywhere, including this forum, and couldn't find a tutorial. I tried a tutorial on YouTube for the Artix 7, and I'm unable to generate a bitstream. I get this critical warning: [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port reset_0 can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["c:/Users/curti/XilinxProjectsCurtis/HelloWorld_hw/HelloWorld_hw.srcs/sources_1/bd/HelloWorld_design/ip/HelloWorld_design_rst_clk_wiz_1_100M_0/HelloWorld_design_rst_clk_wiz_1_100M_0_board.xdc":3] And I get these errors: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. [DRC UCIO-1] Unconstrained Logical Port: 3 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_0, diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. I'm a new user of Vitis, and relatively new to Vivado. Can anyone offer suggestions on how to correct the errors? Or, better yet, where can I find a tutorial that works to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? My thanks in advance for any suggestions, Curtis
  7. Hi im beginner on vivado, i have some troubles to interface the pmod wifi on zybo board. have you any tutorial how to do that on zybo board ?? thanks for your response
  8. Hello I tried HelloWorld example in Vitis and Vivado 2019.2 and this worked well until programming FPGA. Because I have only one USB cable to connect into zedboard PROG port or UART port, I ran a HelloWorld program with "RunAs -> Launch on Hardware(System Project Debug)" with connecting cable to PROG port and reconnected to UART port to receive outputs from zedboard. However, I got weird results(e.g. there is no outputs or there is outputs but garbled). After that, I borrowed a cable from my friend and also connected it to zedboard, and I rerun program and got appropriate outputs. My question is whether I must have two cables to connect two ports when programming FPGA and run program by jtag. If not, please tell me how to do that.
  9. Hi, I asked this on the Xilinx forums too, but so far no one has answered. Maybe someone here can help. I bought a arty-7z-20, so I could learn more about FPGA's. I downloaded Vitis+Vivado 2020.1, and followed some tutorials (for example this one https://nuclearrambo.com/wordpress/programming-the-zynq-7000-with-vivado-2019-2-and-vitis/) but they all have the same basic steps. The Vivado side is clear, I can generate a bitstream and export it to a board. I can also create the HDL wrapper, and export the xsa file. But now when I open Vitis, I should create a new platform project, or create a new application project depending on the tutorial I'm following. But in both I import the xsa file which was created using Vivado. Now when I try to create the project and 'create a new platform from hardware', then select the generated xsa file, it always take about 10-15 minutes saying 'reading hardware specification', then fails saying I need to select the processor type. But there are no processors available. How can I add processors to the list? Do I need to download more files somewhere? I've tried this on Win10, and also Linux. Both the same result. So it's probably just something I've done, but I don't know. I'm a bit lost now. Any hints or tips? Thanks!
  10. Hello, I have a NetFPGA 1G-CML board and in my new project I will have to use Vitis Accelered Libraries. So, I would like to know if I can use Vitis Accelerated Libraries on a NetFPGA 1G-CML board. If I can't use it on NetFPGA 1G-CML, what would be the best board option? Thank you
  11. i get the message, "Vitis launch failed" when select Tools > Launch Vitas. I'm assuming that Vitas is a substitute for SDK. I've tried everything: Uninstalled / Re-installed Vivado 2019.2.1 Started a new project from scratch Looked for solutions in Xilinx and Digilent Forums I'm trying to run through the tutorial: https://reference.digilentinc.com/vivado/getting-started-with-ipi/start Section 6.3 fails: File > Launch SDK does not appear in the pull down menu I'm running the tutorial on the Nexys A7 100T No solutions can be found. Questions: Digilent: Can you update the tutorial to correct the SDK section? Is there a tutorial or app note for Vitis? My gratitude in advance for any help with this. PS. The Digilent Nexsys A7 demo program works. And, I am able to run the blinky program successfully.
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