PMOD AD1 FPGA bitstream genatation issues

[amilashanaka]

I have trying  to interface PMOD AD1 to CoraZ7 , board but im facing issue with genarating bitstream ,

ERROR 

Implementation

Write Bitstream

DRC

Pin Planning

[DRC NSTD-1] Unspecified I/O Standard: 8 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin3_io, ja_pin4_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

[DRC UCIO-1] Unconstrained Logical Port: 8 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin3_io, ja_pin4_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

[JRys]

I suspect you forgot to constrain the pins used by the PmodAD1_01.  Go to Sources, select Constraints, and add a constraints file. Open the file and copy the constraints below. Please pay close attention to the ja_pin#_io numbers, as they are not in order. 

## Pmod Header JA
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja_pin1_io }]; #IO_L17P_T2_34 Sch=ja_p[1]
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja_pin2_io }]; #IO_L17N_T2_34 Sch=ja_n[1]
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja_pin3_io }]; #IO_L7P_T1_34 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja_pin4_io }]; #IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja_pin7_io }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja_pin8_io }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja_pin9_io }]; #IO_L22P_T3_34 Sch=ja_p[4]
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja_pin10_io }]; #IO_L22N_T3_34 Sch=ja_n[4]

[amilashanaka]

Thanks for replying  @JRys

its working fine  

Edited Monday at 02:20 PM by amilashanaka

[amilashanaka]

any one can help me invalid command name "ps7_init" error in sdk for above project