Search the Community

Showing results for tags 'fpga'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

  1. Hi! I'm new to FPGAs and find the Xilinx Installation process quite daunting. The installation guideline on your website is fine, but it does not recommend specific versions of Vitis/Vivado for your boards. Installing the latest version seems to not be a good idea, because certain projects on a board aren't forward compatible. Could you maybe add a table where it states which version you recommend for which board? I'm using the Basys3, and I'm gravitating to 2020.1., but am not sure. Thanks! Sebastian.
  2. Hi, I am having a problem in programming my FPGA. There was no problem in synthesis, implementation and generating bitstream. However, I got these errors: "[Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. [Labtools 27-3165] End of startup status: LOW". After generating .bin file instead of .bit file, I got rid of the first error [Labtools 27-3303]. However, I stil cannot program the FPGA because of the second error [Labtools 27-3165]. I have tried different versions of vivado, different BASYS3 FPGAs, different computers, and cables, but I can't solve it. I don't get these errors in my other codes but only in designs using VGA port of the FPGA.
  3. Hi, In my company, we use Arty7-100T, lately we need to change a voltage domain at least of one bank of FPGA. It is not important which FPGA is mounted on Development Board (Spartan,Artix or Virtex), but it is very important the capability to access to some pin where i change externaly the Bank voltages. Do you have some similar product?
  4. Hey, we are working on a senior design project and to set up a xilinx zeboard we are looking to upload the hello world on to the zinq700. There is something wrong with the UART drivers and were getting this error above. Also pictured below. When we uninstall the driver that claims to be intsalled when we connect the device, and reinstall it. However the UART light remains yellow and ultimately shuts off as soon as we connect the comm port through the sdk, it the LED shuts off. Does anyone have any clue about this issue?
  5. Hello everyone I am selling my almost brand-new Xilinx Nexys 3 Trainer Board w/ Spartan 6 FPGA. I've only used it for about 1 week and it is in absolute Mint condition. I am choosing to sell it because my new job at a startup uses Altera's line of products so I will be getting an Altera FPGA Unfortunately I just got my Nexys 3 so I am try to get whatever money I can for it. A link to this product on the Digilent site can be found below: https://store.digilentinc.com/nexys-3-spartan-6-fpga-trainer-board-limited-time-see-nexys4-ddr/ As you can see, it's worth $270 on the website, the total comes to over $300 if you order it from the store. I was hoping I could get around $200 if possible but am definitely open to haggling depending on the demand. Please let me know if you are interested! This is a great board to build projects and can do a ton of things! Inbox me or comment here
  6. Hello all, I have a question regarding FPGA performance vs GPU (I've reviewed it). I’m trying to recover lost bitcoins that I mined in the early days. I knew it was important to keep the private key but in the end I somehow managed to lose my private key but I still have 24 out of 32 bytes of my private key, found on half a piece of paper when I printed that private key back in 2012. So I have 24 bytes out of the total 32 bytes of my private key. I can only recover this by brute forcing. But I’m not familiar with FPGA and I’m totally unsure how fast they would be able to do these calculations. The required calculations would be incrementing a 256 bit number (starting at the lower boundary of the 24 bytes out of the 32 I have), doing the elliptic curve calculation in order to get a public key and then ripemd160(sha256(publicKey)) and compare the resulting hash160 with my address hash160. If they are equal I found my private key and I can recover my bitcoins. Do you think an FPGA like this could do this in a reasonable time? I don't mind if it takes a year for example but there is no point in doing this if it takes > 100 years... I’m trying to figure out if it’s worth going with an FPGA for this in order to recover +- 110 BTC. Maybe I need too many FPGA’s and it might not be worth it… Or do you think high end GPU’s like an nvidia 1080TI will be better suited for the job? If you think an FPGA can certainly be used for this. What kind of FPGA am I looking at, how much do they cost and how many would I need? Thank you for your time.
  7. YakirP

    Pmod wifi SDK problem

    Hi i'm using Vivado 2018.2 + Zedboard, my goal is to use the WiFiScan from the examples attached to Pmod WiFi folder. i have build the project in vivado section and exported it to SDK at that point i'm creating new application project, choose C++ project and select finish. i'm getting the following errors: flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem thanks for the help
  8. I have a lot of Adafruit Sensors like Temperature Sensor, IMU, Pressure Sensors, etc. which are configured to Arduino. Now I want to connect Arduino to FPGA and the FPGA must read the sensor data and detect for abnormalities for control system. Can anyone help me how can I achieve this.
  9. Hello eveyone, I am working on TLC5940 to drive LEDs with FPGA cyclone V DE10; Could any one here help me with a VHDL code to activate leds via FPGA? I would be so gratefull. Many thanks in advance
  10. I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. https://forum.digilentinc.com/topic/8943-pmod-as-input-and-output-gpio/ #Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }]; set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je_pin4_io }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je_pin7_io }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je_pin8_io }]; set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je_pin9_io }]; set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je_pin10_io }]; I am able to control the GPIO pins of port JF on the Zybo Z720 using the following code, how do I edit this so that I am able to turn on/off LEDs using the Pmod port JE instead. #include "xil_cache.h" #include "xparameters.h" #include "stdio.h" #include "xparameters.h" #include "xuartps.h" #include "xtime_l.h" #include "xgpiops.h" #include "sleep.h" #include "xil_io.h" #include "xil_types.h" #include "xil_printf.h" #include "sleep.h" #include "stdlib.h" #include "string.h" #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) #define TIMER_FREQ_HZ 100000000 #define MAX_WIDTH 320 #define MAX_HEIGHT 240 #define MAX_BUTTON 16 #ifdef __MICROBLAZE__ #define HOST_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_BASEADDR #define HostUart XUartLite #define HostUart_Config XUartLite_Config #define HostUart_CfgInitialize XUartLite_CfgInitialize #define HostUart_LookupConfig XUartLite_LookupConfig #define HostUart_Recv XUartLite_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->RegBaseAddr) #include "xuartlite.h" #include "xil_cache.h" #else #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #include "xuartps.h" #endif #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define BLOCK_SIZE 40 void startup(); XGpioPs_Config *ConfigPtr; XGpioPs output; int main() { startup(); while(1) { XGpioPs_WritePin(&output, 13, 1); //led on (pin 1,2,3,4) XGpioPs_WritePin(&output, 10, 1); XGpioPs_WritePin(&output, 11, 1); XGpioPs_WritePin(&output, 12, 1); } void startup(){ //initialize pins for JF ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID); XGpioPs_CfgInitialize(&output, ConfigPtr, ConfigPtr->BaseAddr); XGpioPs_SetDirectionPin(&output, 13, 1); XGpioPs_SetOutputEnablePin(&output, 13,1); //pin1 JF1 XGpioPs_SetDirectionPin(&output, 10, 1); XGpioPs_SetOutputEnablePin(&output, 10,1); //pin2 JF2 XGpioPs_SetDirectionPin(&output, 11, 1); XGpioPs_SetOutputEnablePin(&output, 11,1); //pin3 JF3 XGpioPs_SetDirectionPin(&output, 12, 1); XGpioPs_SetOutputEnablePin(&output, 12,1); //pin4 JF4 }
  11. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  12. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  13. Div_01

    Nexys2 FPGA board

    Hi, I am a newbie to FPGA. Does the Xilinx Spartan 3E Nexys2 FPGA board contain internal ADC and DAC? If yes, which are the ports for it? Thanks & Regards, Divya
  14. Dear all In vivado design flow in setup debug step I am seeing multiple netlist for only three bit register "state". How can i identify my original signal to debug my design thank you
  15. Hi Digilent Masters, I'm starting to work on a mini project which reading back PmodAD2 VinX data from Arria 10 FPGA dev kit through I2C interface. I'm using Quartus to develop the code, and enabled weak pull up resistor on both SCL & SDA in Quartus The Vcc is connected with 5V and Vin1 - Vin4 are connected with inputs which have max 1.8V. When I measure my SCL with DMM, it shows only 1.4V when HIGH and drops to 0.3 when SCL goes LOW. From the PmodAD2 schematics, it tells me this is definitely not meeting the requirements. What did I do wrong? FYI, I'm new to FPGA design Would be appreciated if anyone can offer their insights on this issue. Regards, Lucas Kang
  16. Hi everyone, so I have a atypical question about J17 port. So accidentally I damaged it, because the board fall and the micro usb cable was connected to PROG port so the board throws the port and causes a physical damage on it. I want to repair it, resoldering the port, because it’s more practical carry a Micro USB cable instead a JTAG to USB converter to program. So if you can help me with the verification of the connections. For example the USB OTG port J13 looks like all the pines are used although the UART port J14 looks like only uses 4/5 pines. I attach the photo of the crime scene and if someone could help me about the connections of the died points. Thanks a lot. ??
  17. I use Xilinx Spartan3E chip to design a SDRAM data storage module, I put the global clock through ODDR2 to output a clock to the SDRAM for data reading, writing and sampling, but I found that I output this clock 80M when the voltage swing is only 500mV, the higher the frequency, the smaller the voltage swing. And I want to push the SDRAM clock to 140M, how to solve this problem? FPGA operating conditions: BANK voltage: 3.3V
  18. How to download Digilent FPGA family development kits such as Nexys, Basys, Atlys, Genesys, etc.
  19. I'm trying to use a VDMA tutorial. I have a ZED Board and I'm using VIVADO 2019.1 Every time I run the SDK, it shows nothing on the terminal. After that I tried to boot from the SD card and it also shows nothing. PS: I checked that I'm using the right terminal
  20. Has anyone had troubles with the PMOD SD Flash Internface where the 10k resistors are too big for the VCU118 board. We may have to create a new PMOD as the 10k causes excessive delay in the ramp above a certain frequency.
  21. How can I access Ethernet port of any FPGA to transfer data from PC to FPGA and vice versa.
  22. I’m trying to debug a program Factorial.c on the Nexys A7 50T FPGA board using PlatformIO. I have procured its bitstream file from the GitHub repository. Shown below is the platformio.ini code: [env:swervolf_nexys] platform = chipsalliance board = swervolf_nexys framework = wd-riscv-sdk monitor_speed = 115200 board_build.bitstream_file = D:\STUDIES\NexysFiles\Nexys-A7-50T-OOB-2018.2-1\vivado_proj\Nexys-A7-50T-OOB.runs\impl_1\nexys50t.bit Shown below is the program code: #if defined(D_NEXYS_A7) #include <bsp_printf.h> #include <bsp_mem_map.h> #include <bsp_version.h> #else PRE_COMPILED_MSG("no platform was defined") #endif #include <psp_api.h> #define N 7 int main(void) { int fact = 1; int temp = N; while(temp > 0){ fact *= temp; temp -= 1; } uartInit(); // Initialize UART printfNexys("Factorial of %d: %d ", N, fact); } Using PlatformIO, the bitstream is uploaded successfully on the board: After clicking on “Run Debug”, the compilation is also done successfully: But the debug console fails with the following errors: My current driver used is: I have installed it using Zadig and have also tried reinstalling the driver but the same issue persists. Please help me resolve this issue.
  23. Hello Recently I have purchased Digilent PMOD AD2. I want to interface PMOD AD2 with my Xilinx Spartan-6 LX45 FPGA board. For conversion of analog signal into digital format. Could you please help me to do this. should I have to write HDL code of I2C? what is maximum speed of operation of PMOD AD2? -- Thank you Gopal Krishna
  24. Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY. My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE parameter in the Xilinx MIPI D-PHY is 145ns. The DPHY_LaneSFEN.vhd file, which is part of the Digilent MIPI D-PHY, uses a constant named 'kTHSSettle' which is set to 85ns. Even if I setup the Xilinx MIPI D-PHY to use a HS_SETTLE time of 85ns, I still see the 'Start-of-Transmission Error' reported by the Xilinx MIPI D-PHY. The camera setup is done by the Digilent pcam_vdma_hdmi application which configures the camera to run in the standard 1080p30 setup mode (2-MIPI lanes, with 420 Mbps/lane). What are the settings for the Xilinx MIPI D-PHY to decode the 2-lane MIPI signal received from the PCAM 5c camera board?
  25. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick