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  1. Hi there! I'm an electrical engineering student and my group has been thrown in cold water: We have to do an SPI Project where we connect a PMOD-Mic3 to our Basys3 Board and measure the frequencies of sounds by giving the Mic signal out to the onboard LEDs. A lot of LEDs have to light up when the frequency is high (over 500 Hz) and less when the frequency gets lower. [We have to create a Vivado VHDL Project.] We have huge problems understanding the core of the exercise. So far, after hours of research, we were not succesful with anything but especially: Establishing SPI-Communication (Master-Slave) Creating working shift-registers Our question is: has anyone done anything like that and can provide us with tipps/tricks or even a working examplary code? We value copyright and would never copy your work, we just need an idea as we have never dealt with FPGAs, VHDL or SPI before. We would appreciate every answer, thank you all a lot in advance! Your ElectricalEngStudent :)
  2. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  3. Hi, I am having a problem in programming my FPGA. There was no problem in synthesis, implementation and generating bitstream. However, I got these errors: "[Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. [Labtools 27-3165] End of startup status: LOW". After generating .bin file instead of .bit file, I got rid of the first error [Labtools 27-3303]. However, I stil cannot program the FPGA because of the second error [Labtools 27-3165]. I have tried different versions of vivado, different BASYS3 FPGAs, different computers, and cables, but I can't solve it. I don't get these errors in my other codes but only in designs using VGA port of the FPGA.
  4. I am adding data file to SPI flash memory. When I add a simple ASCII file, that's what I get as user data. I would like to convert my ASCII data file to binary or some form that gives me raw data. Is there a file converter utility I can use to convert the ASCII file to a binary file prior to adding it to the configuration .bin file? example.txt
  5. Hello! I have just recently purchased a PModCLS board. After a bunch of hard (fun) work, I have it mostly up and running via the SPI port. As a sample project, and at the kids' suggestion, I am using a mouse (connected to a Basys-3 board) to drive the display to create 'eyeballs' that follow the mouse around, or that change their mood as the mouse moves. It's a fun project, and a fun demonstration of what the board can do. My problem is that I'd like to use the backslash as one of the text-art characters in the eyebrows, and everytime I send the device a backslash a ... foreign character appears. (It looks like a 'Y' with two horizontal bars through it.) I know that the reference manual discusses being able to reprogram characters. Can you tell me if all of the characters can be reprogrammed? In particular, can I reprogram the backslash back into a backslash? Or can I only create some special purpose characters using a limited part of the ASCII character set? Thanks! Dan
  6. In an effort to learn how to move network data to/from an FPGA I have taken the ethernet project, rewrote it in VHDL and ported it to a Basys3. I also added a LOT of comments in the code to help explain the header information required for the packets, and I changed the way the IPV4 checksum was calculated in an attempt to make it more obvious with out it works. I used clock wizard IP to gen the 20MHz clock required for the project. This was all in Vivado 2019.1 but that only matters if you want to use the clock wizard IP that I attached. If you just generate your own clock IP, the vivado version you use will not matter. I learned a large amount (yet just scratched the surface) about ethernet, IPV4, and UDP to allow me to rewrite this project. is a fantastic site, even after it appears to have been abandoned years ago. Thank you so much Jean P. Nicolle for leaving your fantastic site online for us. UDP_Tx.vhd Basys3_Master.xdc clk_wiz_0.xcix
  7. I am looking for a way to output audio out of my Basys3 board. I only need to output monotones. The only sounds I will need to output will be the notes in the typical musical scales along with the octaves. My idea was to use the PMOD connector and use a simple 8-ohm speaker with the positive wire going to a random pin location and the other side to one of the common ground pins. Can anyone tell me if this is a viable method of achieving sound output? I have the code which was given to me by my professor but the code was meant for another board with an audio jack but I know I can do it without a built in audio jack. My main concern is the output impedance of the pmod connector which I don't know. I know I can design an amplifier but if I can avoid that, that would be great.
  8. Is this insane? Can I wire a PMOD port, specifically pins JA10 and JA4 as a differential receive port for a UDP project? The brilliant guy who wrote this on built a circuit to generate a common mode input. If I attempt to wire RD+ and RD- directly to a differential pin pair in the PMOD port, am I wasting my time? Damaging my Basys3? I'm thinking about starting by hooking it up with a project that is designed just to run an ILA and see what happens. I am expecting these receive signals to be plus and minus 2.5v. I would like to wire those pins to an IBUFDS. Please talk me out of this if I'm about to do something very stupid. I fear I am about to embark on one of those "hold my beer" and "hey watch this" moments.
  9. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some basic WiFi telemetry to a design. The ESP8266 module used was under $7 - You can find all the source on my Wiki at
  10. My Basys3 board is not recognized in Vivado. I installed Vivido v2020.2 with little effort (although it took well over an hour). When I connect the USB cable and turn the power on nothing happens inside of Vivido. My board is jumpered for JTAG using JP1 (center pins). If I view the hardware manager it shows "unconnected No hardware target open". Clicking Open target than auto-connect shows no change. Only localhost (0) connected is listed. In Windows10 device manager, I do see 2 USB entries labeled "Digilent USB Device" with a value of, Dual RS232-HS (interface 0) and Dual RS232-HS (interface 1). I have power cycled my computer but no change. I can successfully copy the Project.BIT file to a USB drive and load the board that way after changing the jump. What do I try next to establish JTAG connection?
  11. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <= 0; sclk <= 0; end else begin count <= count + 1; if(count == 1) begin sclk <= ~sclk; count <= 0; end end end endmodule __ `timescale 1ns / 1ps module spi0( input clock, input reset, input send, output sclk0, output reg cs, output reg ldac, output reg din ); reg[15:0] data [3:0]; reg[15:0] count; reg [1:0] sel; sclk sclk_inst ( .clock(clock), .reset(reset), .sclk(sclk0) ); initial begin data[0] = 16'b0101111000010101; data[1] = 16'b1000011111100001; count = 16'd16; cs = 1; sel = 0; end always @ (negedge sclk0 & send == 1)begin if (send == 1)begin if ( count > 0)begin cs = 0; ldac = 0; end if (count == 0)begin cs = 1; ldac = 1; count = 16'd16; end din = data[sel][count-1]; count = count - 1; end end endmodule __ `timescale 1ns / 1ps module spi0_testbench(); reg clock = 0; reg reset = 0; reg send = 0; reg [50:0]counter = 0; reg [16:0] i; wire sclk0; wire cs; wire ldac; wire din; wire[15:0] count; spi0 UUT(clock, reset, send, sclk0, cs, ldac, din); always @ (*)begin #10 if (i >= 127 & i < 129)begin send = 0; end if (i < 127 | i >= 129) begin send = 1; end if (i < 127)begin end end initial begin for (i = 0; i < 1000; i = i + 1)begin clock = ~clock; counter = counter + 1; #1; end end endmodule Green: SCLK Yellow: DIN Blue: CS Pink: LDAC
  12. I'm learning how to generate clocks with XDC files, using the .xdc from the Basys 3 github repository as a starting point. I'd like to change the clock to a very low frequency of 1 Hz, or once per second, so that a LED blinks on and off once a second. The portion of the .xdc file that generates the clock looks like this: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 1000000000.00 [get_ports clk] And the code for blinking the LED looks like this: module oneclock ( input clk, output led[15:0] ); assign led[0] = clk; endmodule I can synthesize, etc but the LED appears constantly lit, although dimmer than normal if I'm not mistaken. Is there a minimum to the generated clock? Apologies for the newbie question, any documentation or things to help me learn would be greatly appreciated.
  13. I tried to do this Pong game project and connect VGA to monitor. But monitor keeps flashing. Video im not sure if this problem appear because i have connected Basys3-> VGA adapter to hdmi -> wire hdmi to mini hdmi. Because my screen has only mini hdmi port.
  14. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOARD_PIN {JB9} [get_ports Pmod_out_pin9_t] set_property BOARD_PIN {JB10} [get_ports Pmod_out_pin10_t] Vivado does finish making the bitstream. I then push on incase it works anyway. In the SDK I get another error. 12:28:33 **** Incremental Build of configuration Debug for project uSD **** make all 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 159832 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 12:28:35 Build Finished (took 1s.389ms) Without really knowing what I'm doing, I read the error and think I need to allocate more local memory to the microblaze. "overflowed by 159832 bytes" I then open up my block design and try to customize the microblaze but see no place in change the memory it is allocated. I used the address editor and increase the allocated memory for the dlmb to 128K and then the ilmb to 128K. If I try 256K for each the validation fails. Then after this I get a slightly better SDK error. 13:13:22 **** Auto Build of configuration Debug for project uSD **** make all 'Building file: ../src/' 'Invoking: MicroBlaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -I../../uSD_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/" 'Finished building: ../src/' ' ' 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 61528 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 13:13:25 Build Finished (took 2s.724ms) My over flow is down to 61528 bytes. I am doing all this by following the IPI tutorial and just adding the PmodSD to it. here and here Thanks FBOARC PS I am using Vivado 2018.2 as that is the version in the tutorial.
  15. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my block design already but it is not available to me as an option in the linker script window.
  16. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  17. Hi there, I connected my Basys3 into my Ubuntu however no led turned on and my computer does not recognizes any device connected to it. Therefore, I'm afraid my FPGA has burned out or my USB-B connector is malfunctioning. Is it possible to change my USB-B part for a new one? Does Digilent provide any support for this kind of situation? Or will I have to buy another Basys 3? PS: I have already tried to connect it with a different cable, connect directly to a USB port in another computer as well, and none of these worked. Best regards, Igor Lima.
  18. I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr cntr_rtl cntr_top cntr_top_struc io_ctrl io_ctrl_rtl And in the project it has to diplay on the 7 segment controlled by the switches : count up / count down / hold / reset options: The priorities for these switches are: 1. reset 2. hold 3. count direction top level VHDL file cntr_top.vhd Port Name Direction Description clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset sw_i(15:0) In 16 switches pb_i(3:0) In 4 buttons ss_o(7:0) Out Contain the value for all 7-segment digits ss_sel_o(3:0) Out Select a 7-segment digit io_ctrl clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntr0_i(n:0) In Digit 0 (from internal logic) cntr1_i(n:0) In Digit 1 (from internal logic) cntr2_i(n:0) In Digit 2 (from internal logic) cntr3_i(n:0) In Digit 3 (from internal logic) sw_i(15:0) In 16 switches (from FPGA board) pb_i(3:0) In 4 buttons (from FPGA board) ss_o(7:0) Out to 7-segment displays of the FPGA board ss_sel_o(3:0) Out Selection of a 7-segment digit swclean_o(15:0) Out 16 switches (to internal logic) pbclean_o(3:0) Out 4 buttons (to internal logic) cntr.vhd clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntrup_i In Counts up if signal is ‘1’ cntrdown_i In Counts down if signal is ‘1’ cntrreset_i In Sets counter to 0x0 if signal is ‘1’ cntrhold_i In Holds count value if signal is ‘1’ cntr0_o(n:0) Out Digit 0 (from internal logic) cntr1_o(n:0) Out Digit 1 (from internal logic) cntr2_o(n:0) Out Digit 2 (from internal logic) cntr3_o(n:0) Out Digit 3 (from internal logic) I will attach also the file to the attachment. Now my code is working and do all the funcitionality correct but there is only one issue which is the DEBOUNCE code part. I didnt use the clk signal for the code and i have to change it. The certain given clock signal has to be used. So can any be give me suggestions how i can correct the debounce concept in the code. io_ctrl_rtl.vhd -code down below: library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture rtl of io_ctrl is constant COUNTVALUE : std_logic_vector(16 downto 0):= "01100001101010000"; signal s_enctr : std_logic_vector(16 downto 0):="00000000000000000"; signal s_2khzen : std_logic :='0'; signal s_1hzen : std_logic :='0'; signal s_2khzcount : std_logic_vector(3 downto 0) := "0000"; signal swsync0 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync0 : std_logic_vector(3 downto 0):="0000"; signal swsync1 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync1 : std_logic_vector(3 downto 0):="0000"; signal swtmp : std_logic_vector(15 downto 0):="0000000000000000"; signal pbtmp : std_logic_vector(3 downto 0):="0000"; signal swdebounced : std_logic_vector(15 downto 0):="0000000000000000"; signal pbdebounced : std_logic_vector(3 downto 0):="0000"; signal s_ss_sel : std_logic_vector(3 downto 0) := "0000"; signal s_ss : std_logic_vector(7 downto 0) := "00000000"; begin -- rtl ----------------------------------------------------------------------------- -- -- Synchronize the inputs -- ----------------------------------------------------------------------------- p_sync: process (clk_i, reset_i) begin if reset_i = '1' then swsync0 <= (others => '0'); pbsync0 <= (others => '0'); swsync1 <= (others => '0'); pbsync1 <= (others => '0'); elsif clk_i'event and clk_i = '1' then swsync0 <= sw_i; pbsync0 <= pb_i; swsync1 <= swsync0; pbsync1 <= pbsync0; else null; end if; end process; ----------------------------------------------------------------------------- -- -- Generate 1 KHz enable signal. -- ----------------------------------------------------------------------------- p_slowen: process (clk_i, reset_i) begin if reset_i = '1' then s_enctr <= (others => '0'); s_2khzen <= '0'; elsif clk_i'event and clk_i = '1' then if s_enctr = COUNTVALUE then -- When the terminal counter is reached, set the release flag and reset the counter s_enctr <= (others => '0'); s_2khzen <= '1'; s_2khzcount <= std_logic_vector(to_unsigned(to_integer(unsigned( s_2khzcount )) + 1, 4)); else s_enctr <= std_logic_vector(to_unsigned(to_integer(unsigned( s_enctr )) + 1, 17)); -- As long as the terminal count is not reached: increment the counter. if s_2khzen = '1' then s_2khzen <= '0'; end if; end if; if s_2khzcount = "1010" then s_1hzen <= not s_1hzen; s_2khzcount <= "0000"; end if; end if; end process p_slowen; ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (s_1hzen, reset_i) variable dbouncecntr : integer:=0; begin if reset_i = '1' then swdebounced <= "0000000000000000"; pbdebounced <= "0000"; dbouncecntr :=0; -- Change clocking the process with signal from sens list. else if (dbouncecntr = 0) then swtmp <= swsync1; pbtmp <= pbsync1; dbouncecntr := dbouncecntr + 1; elsif (dbouncecntr = 1) then if (swtmp = swsync1) then swdebounced <= swsync1; end if; if (pbtmp = pbsync1) then pbdebounced <= pbsync1; end if; dbouncecntr := 0; end if; end if; end process p_debounce; swclean_o <= swdebounced; pbclean_o <= pbdebounced; ----------------------------------------------------------------------------- -- -- Display controller for the 7-segment display -- ----------------------------------------------------------------------------- p_displaycontrol: process (clk_i, reset_i) variable v_scancnt : std_logic_vector(1 downto 0):= "00"; variable v_output : std_logic_vector(3 downto 0):="0000"; begin if reset_i = '1' then v_scancnt := "00"; s_ss <= "00000000"; elsif clk_i'event and clk_i = '1' then if s_2khzen = '1' then case v_scancnt is when "00" => v_output := cntr0_i; s_ss_sel <= "0001"; when "01" => v_output := cntr1_i; s_ss_sel <= "0010"; when "10" => v_output := cntr2_i; s_ss_sel <= "0100"; when "11" => v_output := cntr3_i; s_ss_sel <= "1000"; when others => v_output := "1111"; s_ss_sel <= "0001"; end case; case v_output is --ABCDEFG, when "0000" => s_ss <= "11111100"; --0 when "0001" => s_ss <= "01100000"; --1 when "0010" => s_ss <= "11011010"; --2 when "0011" => s_ss <= "11110010"; --3 when "0100" => s_ss <= "01100110"; --4 when "0101" => s_ss <= "10110110"; --5 when "0110" => s_ss <= "10111110"; --6 when "0111" => s_ss <= "11100000"; --7 when "1000" => s_ss <= "11111110"; --8 when "1001" => s_ss <= "11110110"; --9 when others => s_ss <= v_scancnt & "000000"; end case; if v_scancnt = "11" then v_scancnt := "00"; else v_scancnt := std_logic_vector(to_unsigned(to_integer(unsigned( v_scancnt )) + 1, 2)); end if; else null; end if; else null; end if; end process p_displaycontrol; ss_o <= not s_ss; ss_sel_o <= not s_ss_sel; end rtl; The code for : cntr_top_struc.vhd library IEEE; use IEEE.std_logic_1164.all; architecture rtl of cntr_top is component cntr -- component of cntr port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntrup_i : in std_logic; --counts up if signal is '1' cntrdown_i : in std_logic; --counts down if signal is '1' cntrreset_i : in std_logic; --sets counter to 0x0 if signal is '1' cntrhold_i : in std_logic; --holds count value if signal is '1' cntr0_o: out std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_o: out std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_o: out std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_o: out std_logic_vector(3 downto 0)); -- Digit 3 (from internal logic) end component; component io_ctrl ---- component io_crtl port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntr0_i: in std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_i: in std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_i: in std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_i: in std_logic_vector(3 downto 0); -- Digit 3 (from internal logic) swclean_o: out std_logic_vector(15 downto 0); pbclean_o: out std_logic_vector(3 downto 0); ss_o: out std_logic_vector(7 downto 0); -- Contain the Value for All 7-Segment Digits ss_sel_o: out std_logic_vector(3 downto 0); -- Select a 7-segment digits pb_i: in std_logic_vector(3 downto 0); --4 Buttons sw_i: in std_logic_vector(15 downto 0) ); --16 Switches end component; -- Declare the signals that are used to connect the submodules. signal s_cntr0 : std_logic_vector(3 downto 0); signal s_cntr1 : std_logic_vector(3 downto 0); signal s_cntr2 : std_logic_vector(3 downto 0); signal s_cntr3 : std_logic_vector(3 downto 0); signal s_cntrup : std_logic; signal s_cntrdown : std_logic; signal s_cntrreset : std_logic; signal s_cntrhold : std_logic; signal s_overflow : std_logic_vector(11 downto 0); begin --Instantiate the counter that is connected to the IO-Control i_cntr_top1 : cntr port map (clk_i => clk_i, reset_i => reset_i, -- cntrdir_i => s_cntrdir, --swsync_o(13); cntrup_i => s_cntrup, --swsync_o(13); cntrdown_i => s_cntrdown, --swsync_o(12); cntrreset_i => s_cntrreset, --swsync_o(15), cntrhold_i => s_cntrhold, --swsync_o(14), cntr0_o => s_cntr0, cntr1_o => s_cntr1, cntr2_o => s_cntr2, cntr3_o => s_cntr3); --Instantiate the IO control to which it is connected i_io_ctrl : io_ctrl port map (clk_i => clk_i, reset_i => reset_i, swclean_o(12) => s_cntrdown, swclean_o(13) => s_cntrup, swclean_o(15) => s_cntrreset, swclean_o(14) => s_cntrhold, swclean_o(11 downto 0) => s_overflow(11 downto 0), cntr0_i => s_cntr0, cntr1_i => s_cntr1, cntr2_i => s_cntr2, cntr3_i => s_cntr3, ss_o => ss_o, ss_sel_o => ss_sel_o, sw_i => sw_i, pb_i => pb_i); end rtl; Please waiting for your suggestions. Any help would be great appricated thanks for all. here down below example for debounce but couldnt find to way to implement. ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (clk_i, reset_i) begin -- process debounce if reset_i = '1' then -- asynchronous reset (active high) elsif clk_i'event and clk_i = '1' then -- rising clock edge end if; end process p_debounce; swsync_o <= swsync; pbsync_o <= pbsync; ------------------------------------------------------------ Final Project-Decimal Count -1Hz.rar
  19. Hello, I just bought 35 BASY3 FPGA boards for our Digital Systems class and need to install Vivado Design Suite in 30 computers. However I noticed during the installation process a window prompts on the "Select Installation Type" I have to enter USER ID and PASSWORD. I would like to know if there is a way around to having to create 30 accounts in order to install on 30 computers. I suppose I can try to install using 1 account on all 30 computers. Please help me with the best way to install Vivado Design Suite for my class. Thank you, Marco
  20. It is possible to program the Basys3 to be used as a motherboard diagnostics card ?
  21. Hello, Merry Christmas hope you guys are doing great. I am a beginner in digital design course and i want to implement this xadc demo project from digilentinc reference on my Basys3 FPGA. I'm having problems on the step 4 which is running the project as i can't figure the physical connections to connect to the JAXDC port on FPGA. Can someone confirm if the connections i have done in this picture are right? One last question. When you open the XADC Basys3 Demo project and see its constraints, only package pins i don't understand are these A12,B13 ones. Where are they located on FPGA? I'm assuming there are some internal connections like seven segment decoder have. Any help appreciated. Thank You. Regards, Zain
  22. I'm still relatively new to Verilog and FPGA programming, so I've been struggling quite a bit with this one. The goal of the project here is to play a super basic game of 'blackjack' and I can't quite seem to get the system to work. As a note: The game goal is to get to 21, but a number reasonably high and close to 21 could still win the game based on what the Dealer has. The first few if - else if statements are there to interpret the card input from switches on the basys3, and then decide how much to add to the count based on the 'card' input. The latter if - else statement is there to output either an 'H' or an 'S' to the 7-segment display in order to output whether the player should 'hit' and recieve another card, or if that person should 'stay' and just hold onto the cards they have. For some reason, the board only displays the 'H' value on the 7 segment display, and I have no way to find out if the count is actually incrementing in the program since I can't figure out how to test this outside of the board. Any assistance would be greatly appreciated. As a note: I have checked the constraints file, and everything looks correct. blackjack.v verilog file: module BlackJack(input clk, ace, four, five, six, eight, jack, reset, output clk_slow, reg A, B, C, D, E, F, G, H, wire segEn, segEnd); //slow clock code parameter clkbit = 27; reg [clkbit:0] clk2 = 0; always@(posedge clk) begin clk2 <= clk2+1; end assign clk_slow = clk2[clkbit]; reg count = 0; assign segEn = 0; // enable for the 7-segment display assign segEnd = 1; always @(posedge clk_slow) begin if (count <= 10) //states from start to 10 - card decisions made here begin if (ace) count <= count + 11; //adds 11 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (count <= 11) // states from 11 to 17 begin if (ace) count <= count + 1; //adds 1 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (reset) begin count <= 0; end else begin count <= count; end if (count < 17) begin F <= 1'b0; B <= 1'b0; G <= 1'b0; E <= 1'b0; C <= 1'b0; A <= 1'b1; D <= 1'b1; end else begin A <= 1'b0; F <= 1'b0; G <= 1'b0; C <= 1'b0; D <= 1'b0; B <= 1'b1; E <= 1'b1; end end
  23. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not connected. I've got a few other warnings and errors so I really don't understand what went wrong. If anyone know what the issue is and can help me, that would be awesome! Also I'm looking for an example project for wifi pmod using Microblaze to learn from. I'm attaching some screenshots of my project. thanks, Netanel.
  24. Hello, I new on Basys 3, and I need some examples for programming FPGA. In the resource center there are a lot of them, but the examples are written in verilog. I am using VHDL, so the questión is: Is there the same examples like the resource center written in VHDL?
  25. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You