Genesys2 FMC complete pinout missing in .xdc file

[DanielMtz]

Hi people!

 

I'm working on a project using Genesys2 and I'd like to use the FMC port to get some signals.

 

I have the FMC LPC Pin Header from "I am electronic". Here's the corresponding datasheet

https://fmchub.github.io/projects/FMC_LPC_PINHEADER/Datasheet/FMC_LPC_PINHEADER_datasheet.html

 

I want to use the SMA connectors, corresponding to the signals / FMC pins

signal                       FMC pin

DP0_C2M_P             C2

DP0_C2M_N            C3

DP0_M2C_P             C6

DP0_M2C_N            C7

GBTCLK0_M2C_P   D4

GBTCLK0_M2C_N   D5

 

 

SO MY TASK IS TO FIND THE CORRESPONDING PINOUT TO THE FPGA

I've been checking both .xdc and schematics for the Genesys2 board. FMC connector its divided in 5 bays, J1A, J1B, J1C, J1D and J1E. In the .xdc file I can find the ports from J1A and J1B but NOT the others.

 

Any clue

 

 

 

 

[asmi]

1 hour ago, DanielMtz said:

I've been checking both .xdc and schematics for the Genesys2 board. FMC connector its divided in 5 bays, J1A, J1B, J1C, J1D and J1E. In the .xdc file I can find the ports from J1A and J1B but NOT the others.

 

Any clue

Well add them yourself then. What's the big deal?

[zygot]

I'm not sure what documents you are looking at, but the schematic covers all of the signals that connect the FPGA to the FMC connector on the Genesys2. The master constraints file covers all of the non-transceiver pin location and IOSTANDARD assignments.

The Genesys2 has an HPC FMC connector.

You are saying that you want to use the FMC transceiver signals. For the Genesys2, these are connected to MGT banks. Vivado transceiver IP tends to define MGT pins by MGT quad (bank) rather than pin locations. I imagine that this is why the master constraints file doesn't mention these. Also, there are no other constraints that can be applied to these pins, unlike normal IO bank pin. MGT banks on the Genesys2 are 115 through 118 as shown in the schematics. MGT resources, including clocking, are separate from CLB clocking and resources in Series 7 devices.

Occasionally, as is the case of PCIe functionality and transceiver assignments you may have to over-ride Vivado assignments because, oddly, the PCIe cores don't let you do it when defining the core. This is the case of the NetFPGA-1G-CML board.

I'm a bit mystified as to why you would consult a different document for the LPC FMC connector  to figure this out. Also, the Genesy2 doesn't have any SMA connectors. The KC705 is a K325T board with SMA connectors.

 

Edited September 16, 2023 by zygot