Jump to content

Niranjana

Members
  • Posts

    10
  • Joined

  • Last visited

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

Niranjana's Achievements

Member

Member (2/4)

0

Reputation

  1. I don't think this type of communication is possible. Because the EEPROM am trying to access is based on Quad-SPI Interface, but am trying to access via I2C interface. I might need to use an external EEPROM chip which supports I2C:Example- https://www.electronicscomp.com/at24c256-i2c-interface-eeprom-memory-module?gclid=Cj0KCQjwmvSoBhDOARIsAK6aV7hn7EnbanQaLghuTKA4WcMn3d8TjgbbJyFyM1AOmvgD1CuA3OgkCukaAvZ9EALw_wcB By connecting this to the PL side of FPGA , I can read and write data from PS. Correct me if I'm wrong!
  2. I'm using on board EEPROM(which is present in the FPGA itself). Yes, I realised that I've not instantiated any IP/ module related to EEPROM in the Block design which needs to be connected as slave to the PS IIC_1. I'm not sure on how to instantiate the EEPROM! 2.Even if I do , there is no slave address mentioned for the IIC EEPROM. In the Vitis SDK's given example code , they have mentioned reg. the slave addresses:https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/iic/examples/xiic_low_level_eeprom_example.c#L351 So can the user give their own 7 bit slave address?
  3. Adding to that, I am confused with these settings and configurations of Zynq PS: The I2C1 is configured as EMIO.. But I didn't make any connections with respect to PS-PL IPs...Should I connect them as shown in the below diagram?
  4. Hi @artvvb, Thanks for the quick response. There is no external connection for the board. As the EEPROM is within the FPGA , I tried to run the example code. You're right, I don't wanna write into the the monitor screen. I am not sure about how to keep the EEPROM as output in configurations. Also its respective slave address is unidentifiable. And When I referred : https://support.xilinx.com/s/question/0D52E00006hpQI4SAM/i2c-ip-connections-in-ip-integrator?language=en_US I followed the same to keep PS as Master and AXI -PL as Slave. i2c.xpr
  5. Thanks @artvvb, I'm trying to establish a PS- PL communication thru i2c...for which I'm using an example reference code given in the Vitis SDK. (xiic_low_level_eeprom_example.c) so is it possible? Also, I wanted to know if there's any particular slave address for the same? I went thru the user's guide of the board but I'm unable to find the slave address! I wanted to confirm whether my Block design is functionally correct (in Vivado)
  6. Hi, I'm using Zybo Z7020 board (https://digilent.com/reference/programmable-logic/zybo-z7/start) I'm trying to establish I2C communication from the Zynq to on board EEPROM of the device. When I referred the technical manual from digilent, I happen to find nowhere regarding the presence of on board EEPROM. Is there any onboard EEPROM/flash in the board? Will be glad if you could clarify this.
  7. Thank you for the reply.. Since the previous attempt didn't work out properly ..I'm trying to make PS as master and PL as slave..Are there any proper documentations for the same? And should we write individual codes for the same in vitis?
  8. Hi, I am trying to make PL as slave in a I2C protocol while am using other board as master.. The below IP is what I have created.. Am I correct? I need to make axi_iic_0 as slave.
  9. I am trying to launch a program in Xilinx vitis..But the following error is popping up. I am using Zybo Z7020, and my program is based on connecting PS and PL through UART protocol.
  10. Hi , I am trying to establish I2c protocol between the FPGA board and an external device(a TI board) in which the FPGA board acts as master and sends the data. I created the Zynq processing IP and enabled I2C1 for the corresponding pins. I exported the .xsa file to XIlinx Vitis and coded by referring the example given in the examples directory for i2c_master_polled_example.c. The code is as follows. /****************************************************************************** * * Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * Use of the Software is limited solely to applications: * (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * ******************************************************************************/ /* * helloworld.c: simple test application * * This application configures UART 16550 to baud rate 9600. * PS7 UART (Zynq) is not initialized by this application, since * bootrom/bsp configures it to baud rate 115200 * * ------------------------------------------------ * | UART TYPE BAUD RATE | * ------------------------------------------------ * uartns550 9600 * uartlite Configurable only in HW design * ps7_uart 115200 (configured by bootrom/bsp) */ #include "xparameters.h" #include "xiicps.h" #include "xil_printf.h" #define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID #define IIC_SLAVE_ADDR 0x55 #define IIC_SCLK_RATE 100000 XIicPs IicPsInstance; /* Instance of the IIC Device */ static void i2c_init(); static void datasend(); static void i2c_init() { XIicPs_Config *Config; /* * Initialize the IIC driver so that it's ready to use * Look up the configuration in the config table, then initialize it. */ Config = XIicPs_LookupConfig(IIC_DEVICE_ID); XIicPs_CfgInitialize(&IicPsInstance, Config, Config->BaseAddress); /* * Perform a self-test. */ XIicPs_SelfTest(&IicPsInstance); XIicPs_SetSClk(&IicPsInstance, IIC_SCLK_RATE); } static void datasend() { unsigned char sendbuffer[3] = {0xA,0xB,0xC}; //uint8_t myReadBuffer[3] = {}; //xil_printf("the value at receive buffer before datasend is %X\n",rcvbuffer[0]); XIicPs_MasterSendPolled(&IicPsInstance ,sendbuffer, 3 , IIC_SLAVE_ADDR ); xil_printf("Transferred successfully\n"); } int main() { i2c_init(); datasend(); return 0; } I am unable to receive the data in the slave.. what am I missing?
×
×
  • Create New...