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Found 6 results

  1. Hi there, I am working on a project which requires DDR access through PL (i.e, no PS is part of the project) targeted on Zybo Z7-20 FPGA SoC board. As a part of this implementation, I was looking out for Xilinx MIG wizard settings specific to this board. I couldn't find this information anywhere in the Zybo Z7-20 Technical Reference Manual. I went through the datasheet of DDR component available on this board (i.e., MT41K256M16HA-125) but it's very difficult to search for the information required by Xilinx MIG Generator IP. Could anyone please help me out with the suitable resources for this..? The Arty FPGA board Technical Reference Manual clearly specifies the MIG wizard settings. I am exactly looking for the same information for Zybo Z7-20. Any help in this regard is extremely appreciated! Thanks.
  2. I've started a thread for people wanting to know how to use the DDR memory on their FPGA boards. I want this to be interactive as it's not possible to provide a single demo project that works for all boards and all versions of Vivado. To get this started, I've provided a tutorial in the file XilinxDDR_Tutorial_Part_1.txt. As, the name implies this is just the beginning of the tutorial, but if you get through it, you will have a working DDR design running on your hardware. Not everyone ( perhaps no one? ) will be happy with having to plow through a long text file but there are reasons for why I am presenting this material in this format. Perhaps, I will try and pretty the content up at a later time, if the topic is popular enough. [Update] I've posted part 2 of the Tutorial. You can follow steps to creating a more useful DDR design by reading the file XilinxDDR_Tutorial_Part_2.txt. This isn't the end. [Update] I've posted part 3 of the Tutorial in which we look at performance and simulation. imp_top.v imp_top.xdc XilinxDDR_Turorial_Part_1.txt NexysVideoDdrDemo.vhd NexysVideoDdrDemo.xdc UART_DEBUGGER2.vhd XilinxDDR_Turorial_Part_2.txt YASUTX.vhd NexysVideoDdrTest.vhd XilinxDDR_Turorial_Part_3.txt
  3. Hi, I want to develop a simple subsystem that is shown on the picture below. Basically, I need one producer that would generate a picture(s) and one consumer that would display the picture. The consumer is easier part, it's VGA block that reads the pictures from the memory. I want to use a bigger resolution, so I cannot use BRAM and I have to go for DDR. I'm planning to use MIG for this job. The question is whether I can configure DDR as a dual-port ram (one port for generator and one port for consumer). Is it possible? If not, I think that I have to go with multi-master bus, so the consumer is another master on the bus... Other memories that Nexys A7 has are too small (and I guess also to slow). Any help is appreciated. Thanks, Dannny.
  4. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  5. Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I'm not sure if I should use the BRAM module, the DDR, SRAM... What are the differences of these components and which one would you suggest to use? Finally, would you have a tutorial that goes through the different steps of the implementation? Thanks a lot, NotMyCupOfTea
  6. From the album: HDMI2USB.tv - Firmware for capturing HDMI and DisplayPort via USB and Ethernet

    __ _____ __ _______ ___ __ _________ / // / _ \/ |/ / _/ |_ | / / / / __/ _ ) / _ / // / /|_/ // / / __/ / /_/ /\ \/ _ | /_//_/____/_/ /_/___/ /____/ \____/___/____/ alternative Copyright 2015 / EnjoyDigital florent@enjoy-digital.fr Alternative HDMI2USB gateware and firmware based on Migen/MiSoC [> Supported Boards ------------------ This firmware is supported on the following to boards; * Digilent Atlys - http://digilentinc.com/atlys/ The original board used for HDMI2USB prototyping. Use `BOARD=atlys` with this board. * Numato Opsis The first production board made in conjunction with TimVideos.us project. Use `BOARD=opsis` with this board.

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