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  1. Hi, I’m using a Zedboard and when I run a program in Vitis, weirdly it doesnt work everytime. Inded, for the same program, sometime everything works as expected (uart print are succesfull, gpio: sw and led too) but sometime the done led is blue and the programme does nothing. It’s occurs often when I already did a run and I try to do a second one, but sometimes afer using the board for long it occurs just after power up the board. I try to always build my project before and let the card cool down but sometimes it doesn’t help. When it doesn’t work, many possibilities : The application does absolutly nothing The uart stop in the middle of a printf an error appears like : « Error while launcing program : reset APU.APB AP transaction error, DAP status 0xF0000021 » or « Error while lauching program : no taargets found with « name=~"APU*" ,avalailable targets : 1 DAP (APB AP transaction error, DAP status 0x30000021) 2 xc7z020 » It's the case for all project I have created ... This behavior is very handicapping for my work. If you are any idea please share it ! Regards, Julie
  2. In Vivado (2021.2) I have created a new project for the ZedBoard that includes: MicroBlaze in microcontroller configuration with 128KiB local memory AXI interrupt controller AXI timer AXI GPIO (x2) MicroBlaze Debug Module UARTlite When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively): set_property PACKAGE_PIN Y10 [get_ports {uart_rtl_rxd}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {uart_rtl_txd}]; # "JA4" Now I get the following during placement ("Implementation/Place Design/Pin Planning/IO Standard"): [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs: uart_rtl_rxd (LVCMOS18, requiring VCCO=1.800) and sys_clock (LVCMOS33, requiring VCCO=3.300) All of the Pmod connections for the PL appear to be in Bank 13, which is 3.3v, so I am looking for a way to tell Vivado that I want "uart_rtl_rxd" and "uart_rtl_txd" to be 3.3V, and while I'm at it, add any necessary pull-ups/pull-downs. I found out about the "Pmod bridge" IP and installed the unpacked "vivado-library-zmod-v1-2091.1-2" into the IP repositories, and have tried to add "pmod bridge 1.1", routed the "tx_0" and "rx_0" from the UART Lite as I saw in one example, but can't figure out how to assign the "Pmod_out_0" I end up with to a specific Pmod connector. The tutorial at indicates that the "board" tab should have the Pmod interfaces listed, but they don't appear for the ZedBoard. I have attached the block design that removed the direct connection of the uartlite tx and rx signals to pins and added the Diligent Pmod Bridge IP as "tutorial_1.tcl". I am really out of my depth here. I will continue to seek answers via Google and forum searches, but any suggestions would be appreciated. Thanks. tutorial_1.tcl
  3. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &spi1 { is-decoded-cs = <0>; num-cs = <1>; status = "okay"; spidev@0x00 { compatible = "microchip,mcp25625"; spi-max-frequency = <10000000>; clocks = <&osc>; interrupt-parent = <&gpio0>; interrupts = <0 0x2>; reg = <0>; } }; I can even send and receive messages using `candump` and `cansend`, but the interface behaves strange together with some CAN libraries. E.g. Messages are sometimes not sent, when the library tries to send multiple messages without any delay between them. On the other hand, when I connect the PmodCAN to a RaspberryPi and use same said libraries, everything works fine. So the only difference I can see between the working Raspberry Pi and the "strange" behaving Zynq setup, is the manually defined device tree overlay you see above. Long story short: Is my device tree overlay for the PmodCAN correct, to use it together with the ZedBoard on the JE Pmod connector? Maybe there is even a template somewhere? Based on the issues I have, I suspect something might be wrong with the clock and frequency definitions ...
  4. Hello, Does ZedBoard 4PCam FMC Adapter Demo Design support Petalinux? Regards,
  5. Hi everyone, so I have a atypical question about J17 port. So accidentally I damaged it, because the board fall and the micro usb cable was connected to PROG port so the board throws the port and causes a physical damage on it. I want to repair it, resoldering the port, because it’s more practical carry a Micro USB cable instead a JTAG to USB converter to program. So if you can help me with the verification of the connections. For example the USB OTG port J13 looks like all the pines are used although the UART port J14 looks like only uses 4/5 pines. I attach the photo of the crime scene and if someone could help me about the connections of the died points. Thanks a lot. ??
  6. I'm trying to use a VDMA tutorial. I have a ZED Board and I'm using VIVADO 2019.1 Every time I run the SDK, it shows nothing on the terminal. After that I tried to boot from the SD card and it also shows nothing. PS: I checked that I'm using the right terminal
  7. I need to use the JTAG header to program the Zedboard, since the MicroUSB connector is physically damaged. I cannot find any documentation or forums about how to use the JTAG connector for programming the FPGA, so I am going to ask for your help. I have a basic design in Vivado for making switch 0 toggle led 0. The bitstream is ready to be sent to the FPGA. However, when I try to connect to the hardware, by clicking "Open target", it is unable to connect. When I try to manually connect: I am using Xilinx Platform Cable USB adapter for connecting the JTAG to the computer's USB input: I have the driver installed, and it appears in my list of devices when plugged in, and disappears if I unplug it, and is up-to-date: I suspect the jumpers may not be configured properly? But again I cannot find clear documentation on how to set this up. This is how mine is set up: Here is some information about my computer: I am using Vivado 2016.1, since that is used in a lot of the tutorials. I think the Diligent tutorial uses 2016.2. It also comes with the Zedboard board file, although I downloaded the one made by Diligent as instructed in the tutorial. I hope I have provided enough information. I appreciate any help!
  8. Just got myself a zedboard. says "copyright 2020" on the silkscreen so its fairly new. I'm stepping through the instructions here: I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1.0 (64-bit) because that seems to be the recommended version of tools for that tutorial. I tried a later version and a lot of the screenshots were completely different. When I get into vitis, I select the system project in the Assistant pane, and click the Build button (hammer). I get the following under the "Problems" tab: Description Resource Path Location Type fatal error: xgpio.h: No such file or directory main.c /project_1_app/src line 3 C/C++ Problem make: *** [makefile:38: package] Error 1 Debug /project_1_app_system C/C++ Problem When I look at the Vitis.log tab, I see the following, withi the zed.xsa error at the bottom: 12:45:48 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 12:45:48 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 12:45:48 INFO : Launching XSCT server: xsct.bat -n -interactive D:\workspace\temp_xsdb_launch_script.tcl 12:45:48 INFO : XSCT server has started successfully. 12:45:48 INFO : plnx-install-location is set to '' 12:45:48 INFO : Successfully done setting XSCT server connection channel 12:45:48 INFO : Successfully done setting workspace for the tool. 12:45:48 INFO : Platform repository initialization has completed. 12:45:48 INFO : Registering command handlers for Vitis TCF services 12:45:48 INFO : Successfully done query RDI_DATADIR 12:45:57 INFO : Checking for BSP changes to sync application flags for project 'project_1_app'... 12:46:03 ERROR : (XSDB Server)ERROR: [Hsi 55-1571] The design file D:/workspace/project_1_wrapper/export/project_1_wrapper/hw/zed.xsa is already opened at which point, the Vitis.log stops there. I've seen the "fatal error: xgpio.h: No such file or directory" on other posts this forum and elsewhere, but I have not seen a definitive answer to how to fix it. The only specific "try this" thing I've seen is try refreshing and try going back to vivado and rerun synthesis, implementation, and bitstream. Neither fixed the problem for me. I followed these instructions to download board files: I copied the "new/board files" because instructions say that is for versions later than 2014.4 And when I google for "zed.xsa is already opened", I don't find it anywhere. any help would be appreciated
  9. Hello everybody, I am building a Petalinux v2019.1 project to save images using v4l2 driver. The pipeline is simple which includes Pcam-> MIPI csi2 rx subsystem -> sensor Demosaic -> video frame buffer write When I use v4l2-ctl -d /dev/video0 --set-fmt-video=widhth=1280,height=720,pixelformat=RGB24 --stream-mmap --stream-count=1 --stream-to = test.raw to save the Image. test.raw file is saved however it is of size zero. When asked on forums it turned out that there is issue with output format. According to Pcam reference manual it supports RAW10, RGB565 , CCIR656, YUV422/420, YCbCr422 and JPEG compression. Unfortunately MIPI IP core driver doesn't support RAW 10 format. Is there a way I can change PCam output format to RAW8 ? Thanks in Advance.
  10. Hi, I am following the ZedBoard FMC Pcam Adapter One to Four Camera Demo ( and I am able to stream the video of all 4 cameras as of now . Is there a way to save the video that are being streamed or even saving a single frame as image ? I am using Vivado v2019.1 and Xilinx SDK 2019.1 Thank you
  11. Hi, I want to read analog data from ad1 pmod. For Vivado part, I use digilent pmod ips to connet fpga. For SDK part, I use AD1.h and AD1.c library in examples. My sensor sends to me analog values between 0-3.3V. (This is a heart rate ECG values). During using arduino, all heart beat data can be read. But I use same function for zedboard, Analog values doesnt look like arduino's. How I can configure and fix this problem? As you see ad1-zedboard connection as below.
  12. Hello, i just bought a PmodBt2 ( ) the RN42. What i want to do is to use a Zedboard with PmodBT2 to capture all bluetooth packets that are being transmitted nearby and then analyze them using the PL and PS, so far I've managed to make the model in vivado ( thanks to some help from this forum ) but I'm unable to tell is this project is going to work from now on because I can't find a way to configure the module in this manner based on the documentation and reference manuals ( and ) Any help is much appreciated, thank you a lot in advance and have a great one.
  13. I'm trying to run the PMOD BT2 core on a Zedboard, using vivado 2020.2 ( i have not tried other version to be honest ), later i'd like to use this hardware to work with petalinux and write a driver for the bluetooth module. I've been trying for a week now but i can't figure it out, i've read some related posts but i don't know what to do, please help! Here is the block design ( i have used the dilligent Digilent/vivado-library and Digilent/vivado-boards ) I have used the same approach with the OLED and it worked out fine. But with the BT2 it fails, I get these critical warnings as shown bellow. The evil file is this.
  14. Hi All, I am working with a ZedBoard trying to test the output functionality of the Pmod headers. The Pmod headers on this ZedBoard have worked in the past, however, when I try to work with them now it appears that they do not transmit any output data. I've tried this for all four programmable logic accessible headers (JA1, JB1, JC1, JD1). When I assign the output to the LEDs I am able to see the output successfully, but it does not come through the Pmod headers. Here is a very simple HDL file and constraints file that I'm using on my ZedBoard that should produce output on the Pmod headers. HDL File (dut.v): `timescale 1ns / 1ps module dut( output PMOD ); assign PMOD = 1; endmodule Constraints File Contents (constraints.xdc): # ---------------------------------------------------------------------------- # JA Pmod - Bank 13 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN Y11 [get_ports {PMOD}]; # "JA1" set_property PACKAGE_PIN AA8 [get_ports {PMOD}]; # "JA10" set_property PACKAGE_PIN AA11 [get_ports {PMOD}]; # "JA2" set_property PACKAGE_PIN Y10 [get_ports {PMOD}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {PMOD}]; # "JA4" set_property PACKAGE_PIN AB11 [get_ports {PMOD}]; # "JA7" set_property PACKAGE_PIN AB10 [get_ports {PMOD}]; # "JA8" set_property PACKAGE_PIN AB9 [get_ports {PMOD}]; # "JA9" # ---------------------------------------------------------------------------- # JB Pmod - Bank 13 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN W12 [get_ports {PMOD}]; # "JB1" set_property PACKAGE_PIN W11 [get_ports {PMOD}]; # "JB2" set_property PACKAGE_PIN V10 [get_ports {PMOD}]; # "JB3" set_property PACKAGE_PIN W8 [get_ports {PMOD}]; # "JB4" set_property PACKAGE_PIN V12 [get_ports {PMOD}]; # "JB7" set_property PACKAGE_PIN W10 [get_ports {PMOD}]; # "JB8" set_property PACKAGE_PIN V9 [get_ports {PMOD}]; # "JB9" set_property PACKAGE_PIN V8 [get_ports {PMOD}]; # "JB10" # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; Has anyone experienced this faulty behavior? Are they any workarounds or solutions?
  15. Hi I am working on Zedboard LED Demo but I cannot do the 13 step : Programming FPGA with Bit File. It seem to be an error when Zedboard use Microblade instead of ZynQ 7000 series. I also see some mistakes in step 11. The tutorial chooses processor is Microblade which not available when using Zedboard!. I need to run this example for testing my Board. Please help me. Link for the tutorial :\
  16. Hi., Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter. Upto bit stream is done and exported to SDK Successfully. After creating Application and adding files it is showing errors. Kindly help regarding this Version: Vivado 2018.2.1
  17. Hi everyone , I would appreciate if someone could help me solve this strange problem regarding Ethernet transmission of UDP packets in RAW mode with LwIP from Zedboard to Windows PC. I’m using the example project in SDK to test the functionalities of LwIP called udp_perf_client. If I try to use the project as it is (with UDP_SEND_BUFSIZE 1440 ) Whireskark signals that packet are malformed , in fact it seems that “data bytes” are being truncated so are sent less bytes than expected (declared in the costruction of the IP header by LwIP). In the image attached is shown the case of UDP_SEND_BUFFSIZE of 600 bytes for example. Packets arrive successfully only if the size of the Ethernet frame is smaller than 500 bytes. I tried to modify the LwIP options in Board Support Package without success. I can’t address the problem . Thanks in advance
  18. Hi, I want to connect my zedboard to virtual machine (Ubuntu 16.04 64 bit in VirtualBox). When i try to connect throught XMD console to zedboard, it appears that the cable is not connected. Can anyone help me with some hints or advices ?
  19. Greetings, I am looking to get the GERBER AND/OR DXF files for the Zed Board so that I can perform mechanical verification of compatibility and orientation of my MEZZANINE card to the FMC connector of the ZED. Thanks Sean
  20. Hey All, I am trying to make a simple IP block design in Vivado 2018.3 to test the ESP32 PMOD out using AT commands for data transmission. I will attach a picture of my current block diagram to this post. I am getting a critical error (reference below) that says the IP has a packaged board value of "" which is for the Zybo z7 board. My questions are: Q1)Will this design work regardless of this error, as the Zybo and Zed boards are similar and both run off the zynq-7 architecture? Q2)If the answer to Q1 is "no", is there a method of adapting this IP for the Zedboard? (I should be using the latest IP library from Digilent) [IP_Flow 19-4965] IP PmodESP32_axi_gpio_0_0 was packaged with board value ''. Current project's board value is ''. Please update the project settings to match the packaged IP.
  21. Hello I tried HelloWorld example in Vitis and Vivado 2019.2 and this worked well until programming FPGA. Because I have only one USB cable to connect into zedboard PROG port or UART port, I ran a HelloWorld program with "RunAs -> Launch on Hardware(System Project Debug)" with connecting cable to PROG port and reconnected to UART port to receive outputs from zedboard. However, I got weird results(e.g. there is no outputs or there is outputs but garbled). After that, I borrowed a cable from my friend and also connected it to zedboard, and I rerun program and got appropriate outputs. My question is whether I must have two cables to connect two ports when programming FPGA and run program by jtag. If not, please tell me how to do that.
  22. Hi all, I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able to make it work. But I want to buid the project using custom IP's. and I found this project: I used the same (working) VHDL code, the same XDC file, the same setup, and followed his instructions, but for some reason, whenever I try to create custom IP's (with or without AXI), I can't make it work, and the monitor says "no signal". Can anyone please help to figure out what I'm doing wrong here? Thanks, Shlomi.
  23. Hello all, I would like to generate a user-defined clock (1.8V 24MHz) out from the board. (for other devices) After I use a clock_wizard to generate a 24MHz clock and make external, which pin is suitable for assignment? 1) Choose Pmod JA1 (EPP pin = Y11), however, the pin is 3.3V in default. Should I buy a Pmod level-shiftier ? 2) Is there any other proper external IO recommended? Thanks.
  24. Hi, If anyone is interested in retro systems I've started on a port of the Multicomp system. I have a 6502 with basic up and running, you need a pmodps2 to use a keyboard (must be a proper ps2 keyboard). SD Card, Serial access, Z80 and 6809 to follow. Enjoy
  25. Hello everyone, I’m a newbie on working on zedboard, and I want to use my Zedboard to communicate with Pmod MIC3 this time. I did a few researches about how to use the Pmod MIC3, and I think I found something useful in another post, link: I’m really appreciate and thanks for their help, but unfortunately I still have no idea of how to make my Pmod MIC3 to run with my Zedboard. I know Pmod MIC3 is using SPI communication protocol and I read what SPI is, link: But I’m not sure is that Quad SPI is the same as SPI in Zedboard. About the Pmod MIC3, I know that it used a MEMS Mic and an ADC, but I also don’t know how to implement it, like do I need a code or IP cores to handle these 2 components? Here is a simply conclusion of my questions: 1. How to use SPI in Zedboard? (Any pin configuration is required?) 2. Do I need a code or something else to handle the ADC and MEMS Mic in Pmod MIC3? 3. Is it possible to make this project work in .vhdl? Or I need something else? 4. How to getting start with? 5. Importance of IP core I know IP cores is an important thing, but I don’t get a clear idea about it and how it works with Vivado. Any help and reference suggestions is appreciated! Thanks ? !!