FPGA

5,448 questions in this forum

1. ZEDBOARD UART-USB connection problem in linux while using matlab

   Asked by Rohith Gopkaumar, April 1

   • zedboard
   • linux
   • uart usb
   • matlab hdl coder
   0 votes
   0 answers
2. Zynq PWM output issue.

   Asked by CEEJ38, March 27

   0 votes
   1 answer
3. Vitis include directory error/modified DDR code Eclypse Z7 Zmod 1410

   Asked by Xband, March 28

   0 votes
   1 answer
4. Multiple AXI BRAM and GPIO issues using a ZYNQ PS and RISC-V softcore

   Asked by Embargo3198, March 28

   • pynq
   • axi
   • zynq
   0 votes
   5 answers
5. How to write and read data from DDR3 via FIFO generator

   Asked by yosh, March 28

   0 votes
   1 answer
6. ZedBoard. Out-of box project files.

   Asked by markiscarabas, March 28

   0 votes
   0 answers
7. USB104 A7 DPTI Transfer SDK Demo Timeout Error

   Asked by engineer123, March 27

   0 votes
   0 answers
8. FPGA Bluetooth/WiFi Project

   Asked by Razvan1203, March 27

   0 votes
   0 answers
9. Zmod DAC 1411 4096 Sample Limit?

   Asked by timmy, July 6, 2023

   0 votes
   18 answers
10. CMOD A7-35T is possible to generate the clock of 800MHz?

    Asked by SKWen, March 26

    0 votes
    0 answers
11. Negative response of FFT IP in Vivado

    Asked by amna, March 26

    • fft
    • dds
    • vivado
    0 votes
    0 answers
12. Connection from a block external port to the Arty S7 schematic

    Asked by oldViking, March 25

    0 votes
    1 answer
13. Help with DAC Output

    Asked by BOJJJJJJ, March 23

    • zmod dac 1411
    • usb104a7
    0 votes
    0 answers
14. LED failed on Basys 3

    Asked by Neil22, March 20

    0 votes
    1 answer
15. Speed Up DMA Transfer Time for ZMODADC1410 (ADC continous Mode)

    Asked by Jey, March 18

    0 votes
    1 answer
16. Memory write error at 0x100000. APB AP transaction error, DAP status 0xF0000021 and Cannot create listening port TCP:127.0.0.1:3121, and more

    Asked by JCesar, March 20

    • zedboard
    0 votes
    1 answer
17. Generate signals using DDS and analyze them using FFT IP core within the Vivado environment.

    Asked by amna, March 21

    • dds
    • fft
    • vivado
    0 votes
    0 answers
18. AXI DMA Help on Cora Z7-10

    Asked by RyanW, April 14, 2022

    • axi dma
    • coraz7-10
    0 votes
    18 answers
19. Dual core Application in Genesys -ZU in Vitis 2023.2

    Asked by Dharmendra, March 18

    0 votes
    0 answers
20. Spartan-6 XC6SLX9 maximum input clock frequency

    Asked by snabil, March 17

    • fpga
    • spartan6
    0 votes
    0 answers
21. [Resolved] Programming ZyboZ7 fails in Vitis

    Asked by jarteq, March 15

    0 votes
    0 answers
22. Freeze with two subsequent software resets for Arty Z7-20

    Asked by ahmadadam96, March 15

    0 votes
    0 answers
23. Problem in using SPI in ArtyZ7

    Asked by sjx10, March 15

    0 votes
    0 answers
24. Local Memory of the Microblaze overflowed

    Asked by pulkit, November 1, 2021

    0 votes
    8 answers
25. Regarding compatible Vivado Software version range for Arty A7 (xc7a35ticsg324-1L) & power related things.

    Asked by Abhishek, March 14

    0 votes
    1 answer