How to write and read data from DDR3 via FIFO generator

[yosh]

Hello everyone,
I am receiving 56 million bit per minute to my fifo generator and i need to store the data in a big memory which is DDR3, since i am using Arty A7 100T.
Could you please let me know how can i do it? from the fifo, data are going to my microblaze processor to be displayed over ethernet.
Is there any considerations should be taken?
my processor clock is 81.24, and my rtl blocks are 100MHz. Thats why i am using fifo generator for cdc.

What i did so far is configure the fifo generator to independent clock block RAM, and vivado always shows this error message:

[Synth 8-5833] Design has more instantiated block-RAMs than device capacity. Consider targetting to a different part.

 

 

 

 

[asmi]

8 hours ago, yosh said:

What i did so far is configure the fifo generator to independent clock block RAM, and vivado always shows this error message:

[Synth 8-5833] Design has more instantiated block-RAMs than device capacity. Consider targetting to a different part.

Maybe you should stop for a second and actually read and attempt to understand what IDE is telling you? Specifically, you are trying to create a 128x131072 FIFO, which requires almost 17Mbit of BRAM, while your target device (Artix-7 A100T) only contains 4.8 Mbit. Hence the message - "you're requesting more BRAM blocks than your target device actually contain. Consider targeting a larger capacity part, or reduce your demands to something which your target device actually has".