CEEJ38

I am using a Zedboard to output a PWM signal through a Pmod port. I am using the example C code in Vitis to create the PWM. There are functions to set the period and duty cycle, but there is no function to set the Vmax or Vmin. The current output Vmax is 1.16V, and the current Vmin is -2.32V. I need the Vmax to be 5V and the Vmin to be 1.3V. Is this something I need to write my own function for? If so, any ideas on where I should start? I read online that this could be controlled by manipulating clock frequencies, but I don't believe this is true. Could changing the I/O standard of the pin change the output? Any advice would be greatly appreciated. Thanks

Got it makes sense. Thanks for your help.

@artvvb Thank you for your reply. This is super helpful. I have implemented all the code in Vitis in C. I may check out the other ways you suggest implementing it, too. I had a question about how much of the Vitis code runs off the processor vs. how much is implemented behind the scenes onto the FPGA PL side. I think Vitis has HLS, so it should convert some to HDL, but is there any way to know what is running on either the PS or PL side?

Is the answer converting the C code to Verilog and running the code in Vivado instead of Vitis? Apologies if the question is basic. I am a student studying independently and could use the help. Thanks

I am currently using a PmodAD1 with code in Vitis as an ADC. The code reads the digital value obtained by the Pmod and writes it to the serial monitor. I intend to utilize this value to generate a PWM signal, with the duty cycle adjusting according to the input changes. The Pmod is currently operational, and I can generate a PWM signal in Verilog in separate projects. Modifying the duty cycle in the PWM Verilog code requires regenerating a bitstream and reprogramming the device each time. How can I integrate these components to have the PWM automatically update based on the Pmod's input? Here is my block design: Here is my Verilog pwm code:

Hi @artvvb, thanks for your reply. I was able to successfully constrain the Pmod. Do you know how I can find the right I/O standard. I was have been using LVCMOS18 but cannot find documentation for the Pmod AD1 that says which I/O standard to use. The Zedboard Master xdc says that 1.8 is the default but the Pmod reference manual says that the AD1 must have a external power between 2.35 to 5.25 V. Does this mean I need to be using LVCMOS33?

I am new to Pmods and am having an issue connecting the Pmod AD1 IP with a port on the Zedboard. I have seen from tutorials to connect the Pmod to a port in the board tab to the left of the block design. However, I do not see the Pmod folder in the board tab. I have made sure to connect the full vivado-library-master to the IP repository. I will include pictures below for reference. Please let me know if you have any suggestions.