ahmadadam96

Hi, I am using the Arty Z7 board equipped with a Zynq dual core chip. I followed this guide to utilize the second ARM core https://www.hackster.io/whitney-knitter/dual-arm-hello-world-on-zynq-using-vitis-9fc8b7. Unfortunately, I found a strange issue. If I perform two software resets, the first reset works fine, but the second results in the device not booting properly. This is important for me because I intended on using a watchdog to reset the board if it freezes. So two watchdog resets will leave the device not operating. I isolated the problem to this line of code. Removing it means any number of resets work successfully. Unfortunately, it means that the second ARM core cannot boot (since it needs to be booted by the first one). Xil_SetTlbAttributes(0xFFFF0000,0x14de2); The line is intended to disable the cache for the onchip memory shared between the two devices. I have been trying to fix the issue for days now, and I am completely stuck. The same behavior occurs also if I replace the line with "Xil_DCacheDisable();".