Jump to content

Search the Community

Showing results for tags 'axi dma'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 2 results

  1. Hello anyone, I have been trying to get a simple AXI DMA transfer for the PL to PS on my Cora Z7-10 working for a while now. I have followed many tutorials and guides and for some reason I'm just not getting any results. I'm really hoping someone here can help me out with this, as I have been stuck on trying to get this to work for a long time now. The C program seems to get stuck waiting for XAxiDMA_Busy after I call XAxiDma_SimpleTransfer(&AxiDma, (UINTPTR) StreamBuffer, 4, XAXIDMA_DEVICE_TO_DMA). All other calls setting up the PL DMA engine seem to return as successes. I have an arbitrary stream of data being generated by an AXI stream module that just counts up 1 from 0 every transfer. I'm going to input a lot of pictures here in hopes that it might help anyone who wants to take a stab at helping me here. My data generator has 32 bit output and counts up to 31 from 0. I have wondered if there was a problem with tlast, in how the DMA engine considers packets, so I tried using tlast at the end of the 32 word stream and I also tried tying it high. Above is my block diagram for this system. The data generator streams to a FIFO which then streams to the AXI DMA and that's about it. I have the sys_clock coming in at 125MHz which enters the clock wizard and comes out at 100MHz. Here is the data_gen sim with tlast. (This module only, not connected in block diagram; however, I have simulated both of these designs hooked up to a stream data-fifo and they passed the data through just fine, so I don't think it's my handshaking but I'm not ruling out out the possibility that I screwed up another part of the streaming protocol). I also tried tying tlast high for the whole stream as well in the full implementation. The configuration I have for the DMA is fairly stripped down and here is the way I configured it in Vivado. The code I have is fairly straight forward. I lookup the config which returns success as do all the other cases. It gets stuck during the loop checking if the DMA is still busy, and from the debugger I can see that no data was ever transferred into the DMA. I also used to have a print statement in the wait loop to see if any of the values changed in the StreamBuffer array. #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xaxidma.h" #define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID int main() { init_platform(); xil_printf("\n\r"); xil_printf("AXI DMA Self Test\n\r"); XAxiDma AxiDma; XAxiDma_Config *CfgPtr; int Status = XST_SUCCESS; CfgPtr = XAxiDma_LookupConfig(DMA_DEV_ID); if (!CfgPtr) { xil_printf("Case 1: Failure\n\r"); } else { xil_printf("Case 1: Success\n\r"); } Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr); if (Status != XST_SUCCESS) { xil_printf("Case 2: Failure\n\r"); } else { xil_printf("Case 2: Success\n\r"); } Status = XAxiDma_Selftest(&AxiDma); if (Status != XST_SUCCESS) { xil_printf("Case 3: Failure\n\r"); } else { xil_printf("Case 3: Success\n\r"); } XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE); xil_printf( "HasStsCntrlStrm : %u\n\r" "HasMm2S : %u\n\r" "rHasMm2SDRE : %u\n\r" "Mm2SDataWidth : %u\n\r" "HasS2Mm : %u\n\r" "HasS2MmDRE : %u\n\r" "S2MmDataWidth : %u\n\r" "HasSg : %u\n\r" "Mm2sNumChannels : %u\n\r" "S2MmNumChannels : %u\n\r" "Mm2SBurstSize : %u\n\r" "S2MmBurstSize : %u\n\r" "MicroDmaMode : %u\n\r" "AddrWidth : %u\n\r" "SgLengthWidth : %u\n\r", CfgPtr->HasStsCntrlStrm, CfgPtr->HasMm2S, CfgPtr->HasMm2SDRE, CfgPtr->Mm2SDataWidth, CfgPtr->HasS2Mm, CfgPtr->HasS2MmDRE, CfgPtr->S2MmDataWidth, CfgPtr->HasSg, CfgPtr->Mm2sNumChannels, CfgPtr->S2MmNumChannels, CfgPtr->Mm2SBurstSize, CfgPtr->S2MmBurstSize, CfgPtr->MicroDmaMode, CfgPtr->AddrWidth, CfgPtr->SgLengthWidth ); xil_printf("AXIDMA HasSg: 0x%08x\n\r", AxiDma.HasSg); //-------------------------------------------------------- volatile u32 StreamBuffer[256]; for(int i = 0; i < 256; i++) { StreamBuffer[i] = 0; } while(!XAxiDma_ResetIsDone(&AxiDma)) {} Status = XAxiDma_SimpleTransfer(&AxiDma, (UINTPTR) StreamBuffer, 4, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) { xil_printf("Case 4: Failure\n\r"); } else { xil_printf("Case 4: Success\n\r"); } int DMA_Busy_DevToDMA = 1; int DMA_Busy_DMAToDev = 1; while(DMA_Busy_DevToDMA || DMA_Busy_DMAToDev) { //Wait //xil_printf("Waiting\n\r"); DMA_Busy_DevToDMA = XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA); DMA_Busy_DMAToDev = XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE); } for(int i = 0; i < 100000; i ++) { } xil_printf("DMA StreamBuffer Test Data\n\r"); for(int i = 0; i < 16; i++) { xil_printf("0x%08x: %d\n\r", &StreamBuffer[i], StreamBuffer[i]); } xil_printf("Successfully ran AxiDMASelfTest Example\r\n"); cleanup_platform(); return 0; } Here is the serial output I get showing that it gets stuck waiting forever for data to transfer and never transfers anything. Case 1 is the success return of CfgPtr = XAxiDma_LookupConfig(DMA_DEV_ID); Case 2 is the success return of Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr); Case 3 is the success return of Status = XAxiDma_Selftest(&AxiDma); Case 4 is the success return of Status = XAxiDma_SimpleTransfer(&AxiDma, (UINTPTR) StreamBuffer, 4, XAXIDMA_DEVICE_TO_DMA); I also print out the configuration pointer data here. I have determined that the value on the S_AXIS_S2MM_tdata bus has gotten to 31, so it makes me think there is some form of transfer going on there, but I can't figure out why I don't see any values in the stream buffer still. I have tried directly using Xilinx's examples from their website and followed multiple tutorials in the same way the presenter did them. And imported the examples from the drivers in Vitis and changed the DDR base address in them to fit my board with using the correct address as defined in xparamters.h. One of the more recent tutorials I did was with this video below. And the same configuration on my end with the same code seems to still get stuck (This time I can't even tell where as the debugger crazily jumps around in a fashion that makes no sense). No matter what avenue I go it seems like I just can't get the DMA to work, which seems crazy to me. Is there anyone out there who has experienced these difficulties with the AXI DMA engine before? I just can't seem to figure out what's going wrong here despite a couple months of trying many many different things. For anyone who has bothered to read this far down in the post. You're a hero.
  2. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  • Create New...