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Found 6 results

  1. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i found this: /* Definitions for driver GPIO */ #define XPAR_XGPIO_NUM_INSTANCES 1 /* Definitions for peripheral AXI_GPIO_0 */ #define XPAR_AXI_GPIO_0_BASEADDR 0x40000000 #define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_AXI_GPIO_0_DEVICE_ID 0 #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_0_IS_DUAL 1 /* Canonical definitions for peripheral AXI_GPIO_0 */ #define XPAR_GPIO_0_BASEADDR 0x40000000 #define XPAR_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID #define XPAR_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_GPIO_0_IS_DUAL 1 The wizard creates two functions: GpioOutputExample( GPIO_OUTPUT_DEVICE_ID, GPIO_BITWIDTH); GpioInputExample(XPAR_AXI_GPIO_0_DEVICE_ID, &DataRead); input example works (buttons), but output does not (leds) Any help is appreciated! Csaba
  2. Hi, I am currently working with the PmodCAN module and I am trying to make it work inside a bigger design with other AXI IPs. Unfortunately I can not find any documentation about the PmodCAN Vivado IP and the AXI address space. So I have some questions: 1. It is not clear to me, what the use case of the `AXI_LITE_GPIO` interface is. From what I can see, the PMOD interface is pre-defined to be used for the SPI communication with the MCP25625 IC; other SPI PMODS doesn't seem to need it either. I have the suspicion that some of the MCP25625 Pins can be configured as GPIOs in some way, but anything I thought would make sense, does not match with your provided C code examples. Which brings me to my second question. 2. Is there any documentation about the AXI address space and how to use it to configure, send and receive messages? I am currently trying to understand how the IP works by looking at the signals and the VHDL code. Unfortunately this approach is very time consuming and I could get things done much faster, if there is any documentation about the address space. Maybe I am just overlooking something here. To summarize, I would like to ask, if the intention behind the Vivado IP was primarily for demo purposes to use it from C code or not; should I rather implement my own IP to let it directly communicate with other AXI IPs?
  3. I am working on the Cora-Z7s board. My goal is to measure real execution time in seconds for Microblaze Softprocessor. I have added AXI timer IP in the hardware design. But from my understanding AXI timer give us the Clock cycle values. We can devide it by the clock speed to get time (it will be theoratical). But is there any way to get real execution time in Microblaze processoers?
  4. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
  5. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  6. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.