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Found 24 results

  1. Hello, I'm trying to communicate between host (Windows PC) and device (Zybo Z7-20) with micro USB. I have followed the instructions through this link. However, while testing, when I connect the micro USB, 1. No power to Zybo: No recognition 2. Power to zybo: No recognition 3. Power, FPGA program through Xilinx SDK: Recognized as "USB Device" in drive. 4. Disconnect power and re-connect power: No recognition Further info on point 3: When the micro USB is recognized as USB device, it asks to format the drive every time with an error as "E:\ The directory name is invalid". Q1: I understand permission to format is a general procedure, but is it supposed to happen every time I plug in the micro USB? Q2: Isn't it supposed to be recognized as a removable device? When I open device manager, it is recognized under Disk drives as "Xilinx PS USB VirtDisk USB Device" rather than under Ports. Q3: After creating the BOOT.bin and loading into SD Card, JP5 has to be set on SD. Do I follow the same procedure to program after that? That is from Xilinx SDK -> Program FPGA -> Run As -> Launch on Hardware ? I'm a newbie to FPGAs altogether, so apologies if the questions are dim. Thanks in advance.
  2. k-k

    Beginner needs help

    Hello, I am an beginner and use a Zybo Z20 Board Vivado and Vitis. I tryed the Tutorial: Getting Started with Vivado and Vitis for Baremetal Software Projects - Digilent Reference (it works) Now i tryed to add a RTL-Block (VHDL) and connect it with the axi-gpio. Then i want to manipulate it using vitis and a c-code, a LED should shine. But it doesn't work. Is there a tutorial how to connect PL and PS? Can someone help me? Thanks
  3. Hello. I bought an ECLYPSE Z7 board some time ago. I was working on a project where I was interfacing some external peripherals on PMODs of the board. The board has suddenly been turned off and not powering up anymore. Kindly guide me in this. To figure out what is the cause and how can it be corrected. Seems like the custom power IC isn't turning on Thanks
  4. I setup 2 zybo boards, one sends data, and the other receives. The idea is to flip a switch on the sender to turn on an led on the receiving board. Th ey are configured the same, but one is coded to send, and the other to receive. Both boards are connected on two computers and can send/receive using the demo code from the digilent github. After modifying it to send the values from the switches, it does nothing. Here's what I've coded for the Send.txt and for the Receive.txt. Honestly, I'm not too sure what's going on in the code and am trying to make some sense from it. Any help would be appreciated.
  5. Think that you need AXI busses or complicated logic design to use the PL in your fancy ZYNQ device? Well, this demo proves that you don't. Find out how to read and write registers in your PL logic design just by reading and writing a few registers in the PS register set. By routing an unused PS UART to the PL via EMIO you can have a full-duplex data path as well as 6 additional input or output signals. What could be easier?
  6. Hi guys, I bought a zybo board and did a simple hello world project to test the functionality, but it didn't work. Here's what I've done: After exporting hardware and creating sdk projects, I downloaded the bitstream & program into zybo as usual. But the board wouldn't run the program normally(It doesn't terminate and doesn't print helloworld). So I debug the board using xsdb, step by step, and find out that disassembly result is not the same as elf file displayed in SDK. xsd shows that data at 0x100000 is 0xea020049; however, in the sdk, the data should be 0xea000049, as shown in the second picture. If I keep on stpi, since it'll go to the wrong place, CPU will finally goto infinite loop. xsdb% connect tcfchan#0 xsdb% targets 1 APU 2 ARM Cortex-A9 MPCore #0 (Running) 3 ARM Cortex-A9 MPCore #1 (Running) 4 xc7z010 xsdb% fpga -f "design_1_wrapper_hw_platform_0/design_1_wrapper.bit" 100% 1MB 1.8MB/s 00:01 xsdb% targets 2 xsdb% source "design_1_wrapper_hw_platform_0/ps7_init.tcl" xsdb% rst; ps7_init; ps7_post_config; Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended) Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended) xsdb% dow "hello_world/Debug/hello_world.elf" Downloading Program -- C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf section, .text: 0x00100000 - 0x001016eb section, .init: 0x001016ec - 0x00101703 section, .fini: 0x00101704 - 0x0010171b section, .rodata: 0x0010171c - 0x00101733 section, .data: 0x00101738 - 0x00101bab section, .eh_frame: 0x00101bac - 0x00101baf section, .mmu_tbl: 0x00104000 - 0x00107fff section, .init_array: 0x00108000 - 0x00108003 section, .fini_array: 0x00108004 - 0x00108007 section, .bss: 0x00108008 - 0x0010802f section, .heap: 0x00108030 - 0x0010a02f section, .stack: 0x0010a030 - 0x0010d82f 100% 0MB 0.4MB/s 00:00 Setting PC to Program Start Address 0x00100000 Successfully downloaded C:/Xilinx/Zybo/project_2/project_2.sdk/hello_world/Debug/hello_world.elf xsdb% mrd 0x100000 16 100000: EA020049 100004: EA040025 100008: EA00002B 10000C: EA00003B 100010: EA000032 100014: E320F000 100018: EA000000 10001C: EA00000F 100020: F92DD91F 100024: ED3F1FBB 100028: ED6D0B20 10002C: EEF11A10 100030: 00001004 100034: 00001A10 100038: FFFF1004 10003C: EFF1019E elf file contents: Disassembly of section .text: 00100000 <_vector_table>: 100000: ea000049 b 10012c <_boot> 100004: ea000025 b 1000a0 <Undefined> 100008: ea00002b b 1000bc <SVCHandler> 10000c: ea00003b b 100100 <PrefetchAbortHandler> 100010: ea000032 b 1000e0 <DataAbortHandler> 100014: e320f000 nop {0} 100018: ea000000 b 100020 <IRQHandler> 10001c: ea00000f b 100060 <FIQHandler> 00100020 <IRQHandler>: 100020: e92d500f push {r0, r1, r2, r3, ip, lr} 100024: ed2d0b10 vpush {d0-d7} 100028: ed6d0b20 vpush {d16-d31} 10002c: eef11a10 vmrs r1, fpscr 100030: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 100034: eef81a10 vmrs r1, fpexc 100038: e52d1004 push {r1} ; (str r1, [sp, #-4]!) 10003c: eb00019e bl 1006bc <IRQInterrupt> So, the problem is, WHY is the DRAM data partially wrong??? I almost doubt DRAM works normally, but I just bought the board a week ago lol.
  7. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
  8. so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF] > pclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y43 and pclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7 error 2 : [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. error 3 : [Common 17-69] Command failed: Placer could not place all instances here is a link where you should find everything you need if you you want to take a look :
  9. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c
  10. Hello, I am currently developing a project with the ZmodADC1410_Demo_Baremetal of Eclypse-z7. The development environment is vivado 2019.1. I use the lwip software protocol stack in the SDK, RAW API mode, and I want to use UDP through the Ethernet port on the PS side. Send the adc data to the PC (only the data of channel 1), I have now completed the spectrum analysis of the collected data on the PL side based on the adc demo, and then sent the data to the sCH1in [13:0 ] Port of the ZmodADC1410AxiAdapter IP, now I have encountered difficulties in writing the PS-side program. I am confused about how to combine the adc data sent by udp and the adc demo. Is there any relevant example for reference? If not, I hope Digilent can develop a demo for Eclypse-z7 to send adc data via udp. Thank you to anyone that can help!
  11. Hello, I have been successful in running the lwIP echo server on the Zybo Z7 board. However, I want to develop a web server on Zynq. I have gone through the lwIP documentation. However, in the discussion of this topic, I was successful in reading the .bin file from the SD card. Now I want to set up a web server on Zynq so I can command the server to read the .bin file from SD card and store it in the DDR. How do I start working on the web server. I have been searching a lot for the tutorial or anything that could make me understand in a simpler way but I failed to find any.! I also tried understanding the echo server C code in sdk however, after a point it seems too confusing to me. I could even think of modifying the echo server C code to develop a web server with some help, may be. The documentation of lwIP is confusing to me at this point.... Thanks, Shyama.
  12. Hi, If anyone is interested in retro systems I've started on a port of the Multicomp system. I have a 6502 with basic up and running, you need a pmodps2 to use a keyboard (must be a proper ps2 keyboard). SD Card, Serial access, Z80 and 6809 to follow. Enjoy
  13. I am trying to make RAM work on my zybo; however, it keeps failing the memory test, I have tried additionally, I have tried setting up different "memory part" in the settings in vivado according to these reference manuals Do you know what I might be doing wrong?
  14. Hi. I'm using zynq board. I'm a beginner. In my design, I used aurora8b10b IP (with framing mode) . It has AXI_ tdata, tkeep ,tlast,tvalid port. I controlled these signal in my custom logic. What I want to do is reading a frame data from aurora on the PS side. When I see the axi stream fifo, I have similar ports. Can I use this? Or should we use DMA? Please tell me the proper way. thanks
  15. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  16. Hello, I took everyone's advice and I played around with quartus and vivado and honestly I like quartus but I digress. I think I want to get a hybrid SoC/FPGA device to play with instead of plain FPGA. My question is, does the vivado webpack allow for full ARM baremetal development/debugging on the Zynq devices provided by digilent? I found out rather late that Quartus "community" edition doesn't support baremetal development(a ridiculous omission since you're developing an FPGA hybrid but anywho....)
  17. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v
  18. We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
  19. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  20. Hi all, New to the FPGA world as I was tasked a project to help familiarize myself with the programming and function of how FPGAs work. As you can all infer, I am in need of some help on a specific project that I am doing. I am using a ZYBO Zynq 7000 development board, and Vivado 2019.1. What I am trying to do is control an external sensor, or LED through some user interface. I have seen a lot of tutorials that use the on-board LEDs, and if you press a button, it displays that value in binary in a command terminal. My task that I was to do is be able to turn on and off an external LED connected to the ZYBO through the command terminal. It seems I can connect a simple circuit with a LED and a resistor to the PMOD pins that are power and ground. What the command terminal would let me do is then essentially cut power to that pin, therefore turning the LED off. Please let me know if this is probable, and/or how I should task to complete it. Thanks, Russell
  21. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. DigiByteCoin Github Odocrypt Mining Software It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  22. Hello, is there any image processing library that can be used for standalone applications on ZYBO? Thanks, Toni
  23. Hi. I'm beginner of zynq. When I was designing with hdl on spartan6, I drew a timing diagram and designed a state machine to make the desired signal from the desired state. So, I've already designed a state machine. However, I am not sure because I am going to use this state machine in combination with the aurora ip and gpio ip of xilinx. I want to design to interact with gpio1 in some states and gpio2 in others state. (i mean that read value from gpio to PL side in specific state.) For do that, do i design a state machine in custom axi ip? Can i control it only with hdl? Or do I have to control it with C code in SDK? I'm sorry that the question is not clear because I don't know well. Thanks.
  24. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar