FPGA

5,468 questions in this forum

1. ARTY - Is encryption supported on Arty boards?

   Asked by Greg D, February 25, 2016

   0 votes
   5 answers
2. cannot stop synthesis run Advanced I/O Demo on Nexys 4 DDR

   Asked by wintermayr, April 2, 2016

   • nexys 4 ddr
   • vivado
   0 votes
   1 answer
3. power issue on babsys 3

   Asked by jpmfoot, March 20, 2016

   0 votes
   4 answers
4. Getting Started with Vivado guide

   Asked by ColoradoAnalog, April 1, 2016

   • vivado
   • arty
   • getting started
   0 votes
   1 answer
5. xilinx auto detection failed

   Asked by JP, March 30, 2016

   0 votes
   3 answers
6. MUX 2x1 using VHDL

   Asked by Jaiko007, March 30, 2016

   • vhdl
   • fpga
   • mux 2x1
   • xilinx
   • frequency
   0 votes
   1 answer
7. verilog XADC output for module instantiation

   Asked by Shruthi, March 30, 2016

   • xadc
   • instantiation
   0 votes
   2 answers
8. ZYBO PCB request ...

   Asked by debugasm, March 31, 2016

   0 votes
   2 answers
9. lms algorithm LMS algorithm using output from XADC

   Asked by Shruthi, March 30, 2016

   • weight update
   • xadc
   • verilog
   0 votes
   1 answer
10. Revision Control for Vivado

    Asked by sstadlertsi, March 22, 2016

    • revision
    • control
    0 votes
    3 answers
11. Cmod S6 flash loading

    Asked by JP, March 29, 2016

    0 votes
    2 answers
12. jtag-hs1 rev.a with xcf04s, haaaalp!

    Asked by Dthcnnct, March 14, 2016

    • jtag
    • cpld
    • hs1
    • xcf04s
    0 votes
    3 answers
13. HDM In EDID ROM default file?

    Asked by Randall Aiken, March 18, 2016

    • hdmi
    0 votes
    3 answers
14. vhdl Frequency Divider using VHDL

    Asked by Jaiko007, March 26, 2016

    • fpga
    • xilinx
    • frequency divider
    • pwm
    0 votes
    2 answers
15. 'SIM_MONITOR_FILE' placement

    Asked by Shruthi, March 22, 2016

    • sim_monitor_file
    • artix 7
    • basys3
    0 votes
    3 answers
16. Howto Program QSPI from SDK including Microblaze Software?

    Asked by party-pansen, March 8, 2016

    • qspi
    • sdk
    • microblaze
    • program
    0 votes
    3 answers
17. Basys3 with vivado 15.4 problem

    Asked by Billel, March 15, 2016

    0 votes
    7 answers
18. Zedboard Schematics Source Files

    Asked by ncs, March 21, 2016

    0 votes
    1 answer
19. How to interface adxl362 with nexys4 artix 7 fpga

    Asked by Sandeep Reddy, March 22, 2016

    0 votes
    1 answer
20. analog stimulus How to create an analog stimulus file for use with Xilinx XADC ('SIM_MONITOR_FILE') for Artix7 board?

    Asked by Shruthi, March 18, 2016

    • artix7
    • xadc
    • sim_monitor_file
    • xilinx
    0 votes
    1 answer
21. Basys3. How to interface Analog Sensor and Servo motor?

    Asked by aarvy, December 1, 2015

    • basys3
    • artix7
    • xadc
    • adc
    • sensor
    • servo
    0 votes
    9 answers
22. Still problems reading from RAM, VHDL code, test bench

    Asked by TJ, March 18, 2016

    0 votes
    5 answers
23. Reprogram (reset) FPGA

    Asked by aramosam, March 8, 2016

    • fpga
    • nexys4
    • reprogram
    • reset
    0 votes
    6 answers
24. Why VHDL RAM only can write but not read with test bench

    Asked by TJ, March 17, 2016

    • ram not reading
    0 votes
    2 answers
25. spartan-6 LED-BAR on Adept I/O EX

    Asked by HeinzM, March 15, 2016

    • fpga
    • atlys
    • i/o ex
    • led-bar
    0 votes
    1 answer