got by zedboard today

[Navi]

Hi

I am New to using FPGA Boards.

Followed the instruction :

https://www.avnet.com/opasdata/d120001/medias/docus/178/GSG-AES-Z7EV-7Z020-G-14.1-V1.pdf

1.Connect 12 V power supply to barrel jack (J20).

2. Connect the USB-UART port of ZedBoard (J14) which is labeled UART to a PC using the MicroUSB cable.

3. Insert the 4GB SD card included with ZedBoard into the SD card slot (J12) located on the underside of ZedBoard PCB. This SD card comes preloaded with demo software and contains a basic Linux configuration used to implement the demos listed in the later sections.

4. Verify the ZedBoard boot (JP7-JP11) and MIO0 (JP6) jumpers are set to SD card mode as described in the Hardware Users Guide.

5. Turn power switch (SW8) to the ON position. ZedBoard will power on and the Green Power Good LED (LD13) should illuminate

from step 6 I am facing issues can anyone help me out.

alternatively, I tired to install Vivado 2023 and tired to generate a bit stream of simple blink code .I/O pins followed manual and assigned the pins respectively but when generated the bit stream getting 

[DRC NSTD-1] Unspecified I/O Standard: 16 out of 16 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[7:0], and switch[7:0].

[JColvin]

Hi @Navi,

The error you are getting when trying to generate the bitstream is due to the pins that you are using in your HDL / block design are not being properly assigned to the physical FPGA pins via the constraints (.xdc) file.

I'm not sure if Avnet has their own .xdc to go with their board file of the Zedboard, but Digilent has some instructions on how to set up and use the .xdc file available in this HDL only guide here: https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado#adding_a_constraint_file, as well as in this block design based setup here: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design.

Let me know if you have any questions.

Thanks,
JColvin

[Navi]

Hi thanks for replying which version of vivado is better to use as I am seeing SDK software but I was discontinued so if possible can you provide be any guide for it