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Found 20 results

  1. We have a 16 node NetFPGA system with Xilinx Programmers which detects the hardware devices without any issues. We are trying to use Digilent HS3 programmers instead and they do not detect the hardware devices even with all the relevant drivers installed. We have used many of the troubleshooting procedures in forums with similar issues with no solution. Furthermore, we have installed Digilent Adept 2 as well to doublecheck. It does show that the programmer is there, it still doesn't detect the hardware devices. Device is properly identified: $ dadutil enum Found 1 device(s) Device: JtagHs3 Device Transport Type: 00020001 (Transport Type = USB, Protocol = 2) Product Name: Digilent JTAG-HS3 User Name: JtagHs3 Serial Number: 210299B4C076 All the libraries are present: $ /sbin/ldconfig -p | grep ftd2xx libftd2xx.so (libc6,x86-64) => /usr/lib64/digilent/adept/libftd2xx.so libftd2xx.so (libc6,x86-64) => /usr/local/lib/libftd2xx.so libdftd2xx.so.1 (libc6,x86-64) => /usr/lib64/digilent/adept/libdftd2xx.so.1 libdftd2xx.so (libc6,x86-64) => /usr/lib64/digilent/adept/libdftd2xx.so Still, it doesn't detect any hardware devices: $ djtgcfg init -d JtagHs3 Any help in this regard is appreciated.
  2. Just starting with FPGA's and using the Zedboard. I have a simple program that uses switches to turn on/off the leds. When I power cycle the board the program seems to be erased and I have to reprogram the board. How can I make this persistent (I am using Vivado)?
  3. Hi, In my company, we use Arty7-100T, lately we need to change a voltage domain at least of one bank of FPGA. It is not important which FPGA is mounted on Development Board (Spartan,Artix or Virtex), but it is very important the capability to access to some pin where i change externaly the Bank voltages. Do you have some similar product?
  4. Hey, we are working on a senior design project and to set up a xilinx zeboard we are looking to upload the hello world on to the zinq700. There is something wrong with the UART drivers and were getting this error above. Also pictured below. When we uninstall the driver that claims to be intsalled when we connect the device, and reinstall it. However the UART light remains yellow and ultimately shuts off as soon as we connect the comm port through the sdk, it the LED shuts off. Does anyone have any clue about this issue?
  5. Hello, I'm trying to communicate between host (Windows PC) and device (Zybo Z7-20) with micro USB. I have followed the instructions through this link. However, while testing, when I connect the micro USB, 1. No power to Zybo: No recognition 2. Power to zybo: No recognition 3. Power, FPGA program through Xilinx SDK: Recognized as "USB Device" in drive. 4. Disconnect power and re-connect power: No recognition Further info on point 3: When the micro USB is recognized as USB device, it asks to format the drive every time with an error as "E:\ The directory name is invalid". Q1: I understand permission to format is a general procedure, but is it supposed to happen every time I plug in the micro USB? Q2: Isn't it supposed to be recognized as a removable device? When I open device manager, it is recognized under Disk drives as "Xilinx PS USB VirtDisk USB Device" rather than under Ports. Q3: After creating the BOOT.bin and loading into SD Card, JP5 has to be set on SD. Do I follow the same procedure to program after that? That is from Xilinx SDK -> Program FPGA -> Run As -> Launch on Hardware ? I'm a newbie to FPGAs altogether, so apologies if the questions are dim. Thanks in advance.
  6. Hi, I am following the steps from the following tutorial: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi When I try to load the application with the debugger, I get the following error: xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Cortex-A53 #0: EDITR not ready) I am using Vitis 2020.2 and Vivado 2020.2. There is no PL in the design. I have the PL-PS interface disabled. Its just a basic Hello World. The target is Genesys ZU 3eg Rev. D I used both the board file and constraints file from the Digilent repository. How do I load, run, and debug the application over JTAG? regards, Jason I think there might be a problem with the Block Automation in the Genesys Zu 3eg file. After running Block Automation the Address Editor is blank.
  7. Hi , i want to enter analog DC voltage to ZYNQ7020 FPGA Device , which pins of XADC J40 pins i have to use ? i 'll be grateful for any support
  8. Hello everybody, I am building a Petalinux v2019.1 project to save images using v4l2 driver. The pipeline is simple which includes Pcam-> MIPI csi2 rx subsystem -> sensor Demosaic -> video frame buffer write When I use v4l2-ctl -d /dev/video0 --set-fmt-video=widhth=1280,height=720,pixelformat=RGB24 --stream-mmap --stream-count=1 --stream-to = test.raw to save the Image. test.raw file is saved however it is of size zero. When asked on forums it turned out that there is issue with output format. According to Pcam reference manual it supports RAW10, RGB565 , CCIR656, YUV422/420, YCbCr422 and JPEG compression. Unfortunately MIPI IP core driver doesn't support RAW 10 format. Is there a way I can change PCam output format to RAW8 ? Thanks in Advance.
  9. Hi all, this is my first time posting here because I really need the 2019.4 version of the Xilinx Vivado SDK. I deleted it when I updated to the 2020.2 version today forgetting everything I have would be uncomeatable. I went to redownload the 2019.4 version but only the 2019.1 version was available on the website, this also didn't work. (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html) If anybody has it installed or knows where I could get it I would be grateful. I was also wondering if anybody has a contact at Xilinx that may be able to provide it. Thank you everybody I really need the help
  10. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start https://projects.digilentinc.com/arthur-brown/displaying-color-readings-with-the-pmod-color-and-python-ebd794 and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c
  11. Hello Everyone, I am newbie to Xilinx Platform, please provide your suggestion. > Platform: Xilinx SDx 2019.1 Board: Zedboard Host machine: Ubuntu > I have a general question, when a C++ program executes with good result in one platform, but good results are not obtained while executing the same program in Xilinx SDSoC platform without build errors and implemented on zedboard. > In my case, Acquisition program in C++ works perfect in Qt Creator Application with incomming.bin file, signals are acquired. But while implementing and executing the same program in Xilinx SDx on zedboard by providing the same incomming.bin file from petalinux root directory structure, no signals are acquired and also there is no build errors. > Can anyone please suggest, what are the pre-requisites that must be taken before importing the program on Xilinx SDx ? And also is the declaration of variables differs in XIlinx SDx when compared from other platforms ? Thank you
  12. I left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. The computer's device manager shows that something is plugged in, but Adept and Vivado are unable to recognize that a device is connected. I was planning to restore the board to it's default setting on Vivado by using a .bin file but received the following error message: "ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Common 17-39] 'open_hw_target' failed due to earlier err." I used a voltmeter to test the voltage across the on/off switch and was getting around 3.3V but now get 0.003V. When I tested the switches that control the on-board LEDS, the also produced around 0.003V. Is there a solution to help me with this as the board is brand new?
  13. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_consulting/Digilent_Xilinx/Zybo_eval_Xilinx_Zynq/Example_Prjs/Zybo-Z7-20-DMA-2018.2-1/vivado_proj/Zybo-Z7-20-DMA.runs/system_processing_system7_0_0_synth_1/.Xil/Vivado-7036-Rafi-GamePC//incrSyn/system_processing_system7_0_0.genomesNotDumped": no such file or directory Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1045.969 ; gain = 379.242 INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 101 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 07:07:59 2020... ============================ Vivado version: 2018.2
  14. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  15. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  16. tomii


    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting around my home "lab," I've got a few Opal Kelly boards (XEM3001, XEM3005, and a couple others) - I love the FrontPanel system they've developed. I've also got an Arty (35T) and now a Cora (low-end Zedboard), and I'm itching to learn some stuff there. I also do a fair amount of bare-metal embedded when I need to (e.g. Atmel/Microchip microcontrollers), and have also recently been doing some stuff with embedded Linux on the pi platform. Lastly, let's talk about the registration process. Jimminy Christmas, it took me and another engineer 8 tries to get validated! Holy cow, am I st00pid, or what? -Tom
  17. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
  18. Dear sir, I am using xilinx FFT 9.0 IP core in Vivado 15.2 for my application, I am computing 512 point IFFT with cyclic prefix using this IP core but output is not coming correctly. Although most of the output samples are correct but some samples are changing drastically. I am using this IP core in real time mode and giving 512 complex symbol at the input of core on every clock after s_axis_data_tvalid and s_axis_data_tready becomes high. Earlier I have used xilinx FFT 7.1 IP core in ISE14.6 which working fine with same settings and same input data. Kindly help me to debug this IP core
  19. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is always the same -- it intermittently disconnects and fails. The amber LED does however stay lit. In Device Manager I am able to see the FTDI UART. I did also see it enumerate as a Microsoft BallPoint Mouse -- whatever that is. With this exact same setup, PC, Vivado, USB cables, etc, I have been programming the Zybo Z7-20 and the Arty boards with several designs without any such issues. Please let me know if I missed anything and what are the next steps in getting the board replaced or fixed. Thanks.
  20. Wyorin


    I have developed a test system using a Xilinx Spartan 6 and the Digilent JTAG-SMT2 programming module. I can program the device OK but if I include an Chipscope ILA and run the analyser the ILA is not found. I know that the ILA is in the build because I have looked for it using ISE14.7 FPGA Editor. I have turned the JTAG clock speed right down to 125 kHz, but still no joy. Any thoughts?
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