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Found 22 results

  1. Is there a reference example or cookery for using the Macronix QSPI flash as main memory for a Microblaze; e.g. on the CoraS7 which has neither DDR nor SRAM and limited BRAM - the C libraries will easily fill 256+ kBy of memory, the S7-25 has 80 BRAM blocks IIRC (320 kBy). Narrowly the issue is how do you configure Microblaze + cache + QSPI flash (as Mb memory) I can't find an answer ... Martin
  2. hello! I am trying to create a project that uses microblaze and the temperature sensor adt7420 on nexys 4 ddr. I don't know how to configure the xadc core for this job and and what other block I need in my design. Does anyone have any similar project so I can figure it out?
  3. Hi, I trying to build some project by implement the PMOD MTDS using microblaze on Arty A7-35T. I had followed the instructions in the README.txt of PMOD MTDS and the microblaze ip core with the PMOD MTDS ip core is successfully built with bitstream file successfully generated. However, when built the project using VITIS 2020.1, it failed. It show that "undefined reference to mydisp". When I open up the folder, it seem liked the "stdint.h" library file is not recognized by the compiler. Kindly need help on this kind of problem. Thanks.
  4. Hi, I am an professional VHDL/Verilog based system designer. I always admired C/C++ based systems programming(the embedded world). Seems like after so many years I finally got a chance. And here is my problem: I haven't programmed any microcontroller ever. And I need to do a complete Microblaze based design now. I can design block diagram in Vivado, the problem is C/C++ programming and understanding what registers to set for a particular tasks(kinda very different from what we do in Verilog based programming). All I need now a few explained examples of lets say button based interrupts implementations, Timers or Timer based interrupts, UART or something like that. Just few examples. I already have kits with me (Trenz and Arty 7 25) Please help me with that. Any examples, any link or advice is welcome.
  5. I am working on the Cora-Z7s board. My goal is to measure real execution time in seconds for Microblaze Softprocessor. I have added AXI timer IP in the hardware design. But from my understanding AXI timer give us the Clock cycle values. We can devide it by the clock speed to get time (it will be theoratical). But is there any way to get real execution time in Microblaze processoers?
  6. Hi all, I have created a block design in vivado,and generate bitstream successfully.Everything seems to be successful,and then i export hardware and create an application project with "Hello world" template,and i did not change anything. But when i try to program FPGA, i get the following error messages. " ERROR: [Updatemem 57-153] Failed to update the BRAM INIT strings for ./.../*.elf and ./.../*.mmi " I'm pretty sure that i have selected the bitfile that was generated earlier. And here is my block design ,any suggestions?
  7. Hi guys, Please help to get Arty S7 up within Microblaze + DDR3 working together. I've spent a couple weeks to built right configuration where Microblaze that has access to DDR3 - I ve tried numerois examples including in Digilent ones that bit oldy - but no results. Currently I'm using vivado 2020.2 I managed to built stable Microblaze configuration using directly ddr_clk or sys clock but when I 'm trying to use 'ui_clk' of MIG7 as source clock for Microblaze and the rest of design - everithing goes wrong - Vitis says that Microblaze is held in reset. Has anyone managed to get working the project with Microblaze + DDR3 working together for Vivado 2020? Any links.. Thanks in advance
  8. Hello, I checked the tutorials and read the pdf-s on the AXI Interrupt controller. However, i could use come clarification about a couple of things. In Microblaze advanced configuration there's an option to set interrupts to NONE/NORMAL/FAST, or leave it in AUTO mode. Is this setting linked to the AXI interrupt controller creation process? I mean if it run Block Automation, and enable Interrupt Controller, then AXI Interrupt Controller IP is created, but the setting doesn't change in the microblaze settings (for example it stays AUTO/NONE). Does that mean if i want a normal mode interrup controller setup, then i have to set it to normal in the AXI Interrupt Controller, also in the microblaze settings? What are the differences between FAST and NORMAL mode? Docu states: "In this mode, AXI INTC provides the interrupt vector address using the interrupt_address signal, and the processor acknowledges an interrupt through the processor_ack signal." Does that mean that if i have it in NORMAL mode, then it will not send the vector to the processor, and those lines doesn't need to be connected? Does the Interrupt interface on the microblaze and the AXI Interrupt Controller have to be connected in both NORMAL and FAST mode? If not, they communicate over AXI? If i have a timer that is the only interrupt source in my design, and i want a callback function to be called every time the timer sends an interrupt, how can i implement this with the simplest AXI INTC? Can i do this in normal mode?
  9. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  10. hello, i am implementing image processing on Xilinx Basys 3 board for which i am using microblaze. I have created an image processing ip which will be reading and writing data through a DMA to microblaze. But i not not sure which is the right way to connect my DMA to microblaze. If i am using Zynq PS i would be using HP mode or slave ACP pin to connect with my DMA but have no idea how to do the same in MicroBlaze.
  11. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  12. Just like this post here, my out of the box example's ethernet is not working. In trying to follow the guide. Changed link speed to 100 as it said. The echo server isn't working, keeps saying the link is up then down, and my computer keeps connecting then disconnecting. All within about a second, so I don't have nearly enough time to see if anything is working even when it is "connected". So then I tried the peripheral test project, and I got an "AxiEthernet: Rx fifo over run" on the "AxiEthernetSgDmaIntrExample". So I increased the rx buffer in the IP re-customization to the max 32KB, no luck. I added some outputs to try and debug it, added the Axi dma bd ring checks to the tx & rx buffers, both pass. The example also errors with "Length mismatch" as it is not receiving everything it sent. When I do a debug launch I don't get the fifo over run, so either a coincidence or something is acting up. I also have it printing out the lengths of the rx/tx, tx is 1014, rx varies as low as 60 and as high as 216 from what I've seen so far. All the other tests (ethernet dma, timer ctr, timer interrupt, axi intc) passed. When I try unplugging the ethernet cable it hangs on waiting for the bytes to come back which I suppose makes sense. I'll attach my xsa. I've been setting the programming mode to JTAG so as far as I know the builtin example is still sitting there on the QSPI for if I need it. I couldn't get the code to build with 2020.1 even after upgrading everything, so I can't try that as a fix. EDIT: managed to get the echo working by polling the BMSR register and waiting for the negotiation complete bit to be set design_1_wrapper.xsa
  13. I have an old Spartan 3E Starter Kit and I need to develop an embbeded system. Such system targets an acceleration for a specific computation process. https://i.postimg.cc/0QDXmRBb/image.png To do so, I will employ MicroBlaze for the management process connected to a vhdl block which is the piece of hardware that will perform the acceleration itself according to Figure 1. Figure 1 - basic scheme for my acceleration process The design is being done in XPS (the hardware) and in Eclipse SDK (the software). In the C software I will employ a send function which will pass to the acceleration VHDL block. The process will be performed and a receive function will gather the result to be presented, e.g., in the LCD. It is my intention to develop my vhdl block will be specified via "Create and Import Peripheral Wizard". My problem: I donĀ“t know how can I specify my VHDL acceleration block net ports, i.e., if they are external, or how type I can classify them. I have examples of how to connect actual peripherals, such as dip switches, leds, LCD. In all these examples, they are classified as "Make External" ones. I go to the .ucf file, insert the respective information, and everything goes fine. But, in my case, as show in Figure 1, my connection to the MicroBlaze is internal, inside the FPGA. Trying to solve this, I am using a 4-bit integer multiplier as my "acceleration block". This MWE block receives the a and b operands, each one of them with four bits, performs a basic multiplication, and gives an 8-bit result. Any help will be appreciated.
  14. Hi, I am playing with the nexys video user demo. I have changed the bitstream to display an overlay (BITC) instead of mouse pointer, and I can bake the bootloader into the bitstream and write it to the flash. I now want to change the microblaze software, which appears to be at flash address 0xa00000. What format image do I write there? Is it the ascii SREC file? James
  15. dfdias

    AXIQUADSPI-ACL-NEXYS4

    Hi was trying to interface the accelerometer available on the nexys 4 board. But i was not getting any data. Then I mapped the output pins to the JA PMOD header so I could probe them Using an logic analyzer I saw that the sclk and Chip_select were working but the MOSI signal is full of zeroes. I connected an 50MHz clk coming from the clock wizard, and then connected it to the ext_spi_clk and used an scale of 16 so the clk is about 3.16MHz Below is the Block_Design helloworld.c Below is the data I acquired using saleae logic analyzer: I submitted the C files containing the main (helloworld.c) wich is a almost linear copy of the polled example; The accelmacros file has some values with the commands and register addressees of the SPI slave. Do you have any hint of what I am missing? Thanks in advance. accelmacros.h
  16. Billel

    Microblaze sleep mode

    Hello How can I put the Microblaze in standby mode and reduce its power consumption? regards,
  17. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not connected. I've got a few other warnings and errors so I really don't understand what went wrong. If anyone know what the issue is and can help me, that would be awesome! Also I'm looking for an example project for wifi pmod using Microblaze to learn from. I'm attaching some screenshots of my project. thanks, Netanel.
  18. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended offset for CMOS S7? I tried both 0x00000000 and 0x0030000 and could not get the design to work. Kind Regards, James
  19. Dear Support, I am trying to implement a Microblaze in the Arty S7 with 50T FPGA board revision E. (yes Rev E not B). I instantiate GPIOs, Switches, LEDs, pushbuttons, UART and SPI at J7. I want to write c code to control the LEDs and talk to an SPI device. Attached is my implementation in picture format. The design verifies, synthesizes, and implements, but I get timing is negative. ISSUES 1. I am not sure how the GPIOs route from the block diagram to constraint file. I downloaded the constraint file, and uncomment the clock, and GPIO switches, etc...However, in the block diagram net names do not match the constraint file. I don't know how to map them In the case of the clock, I matched the Net CLK_12MHz in the block diagram to the constraint file, but for the GPIO, and others I am not sure I am doing this correctly. 2. Timing fails no matter if I change the CLOCK_OUT from 100MHz, 96MHz, 80MHz. Timing fails. HOW TO IMPLEMENT THE CONSTRAINT FILE TO BLOCK DIAGRAM...They should match no? Please advise how to fix timing, and how to map constraint file. I am sure I am not doing this right. I have watched numerous videos on implementation, and every implementation passes but they don't show how they setup other stuff. ## Clock Signals set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports CLK_12MHz]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports CLK_12MHz]; ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit SPI Header ## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time. set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck # Misc. ChipKit Ports #set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports RESET_N]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] # SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Arty-S7-50-Rev-E-Master.xdc
  20. Hi I am new to microblaze. I have to design an efficient ALU using microblaze in Nexys 4 Anyone can guide through me the procedure ( I know the general guide line) and refer any document to do it Regards Uzmeed
  21. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
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