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Found 20 results

  1. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  2. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i found this: /* Definitions for driver GPIO */ #define XPAR_XGPIO_NUM_INSTANCES 1 /* Definitions for peripheral AXI_GPIO_0 */ #define XPAR_AXI_GPIO_0_BASEADDR 0x40000000 #define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_AXI_GPIO_0_DEVICE_ID 0 #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_0_IS_DUAL 1 /* Canonical definitions for peripheral AXI_GPIO_0 */ #define XPAR_GPIO_0_BASEADDR 0x40000000 #define XPAR_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID #define XPAR_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_GPIO_0_IS_DUAL 1 The wizard creates two functions: GpioOutputExample( GPIO_OUTPUT_DEVICE_ID, GPIO_BITWIDTH); GpioInputExample(XPAR_AXI_GPIO_0_DEVICE_ID, &DataRead); input example works (buttons), but output does not (leds) Any help is appreciated! Csaba
  3. (Newbie here. Sorry if this was covered elsewhere, and I couldn't find it.) I got my simple FPGA design working on Arty S7. Now I wish to program the onboard QSPI (S25FL128SAGMF), so the S7 will self-configure upon power up. I found this Vivado doc about programming and debugging. Chapter 6 covers Programming Configuration Memory Devices. Step 1 is to Generate the bitstream for use with configuration memory devices. Is the same *.bit file (and settings) I already generated to program the S7 directly, or do settings need to change, because I'm going to program it into the QSPI memory? Does Digilent have any Arty S7-specific documentation (or configuration files) for accomplishing this step?
  4. Kind of new to the world of FPGA tinkering. Just bought an ARTY board and the OLEDrgb pmod. Struggling to find some verilog code for the SPI driver, together with some simple demo that I could use with Vivado, perhaps a simple MicroBlaze code snipet that drives the display. I could then use this a base going forward. Does anyone recommend anything here? Thanks Steve
  5. I just completed my first mini-project on my new Arty A7 (my first FPGA). ? On Windows 11 with Vitis/Vivado 2021.2, I have the OLEDrgb working. It's unlikely I did everything the best or most proper way, but it's working. If anyone is interested, I shared a walkthrough with all of the steps I took to get the OLEDrgb working on my A7. Arty A7 & OLEDrgb Pmod Walkthrough All suggestions on how to improve the implementation are welcome. I can update the instructions with any recommendations you may have. Thanks!
  6. memo

    Arty S7 XADC Pins

    Hi there, I hope everyone is safe and doing well, and thank you checking out my forum post; I would greatly appreciate your help :D I was trying to get the XADC working on the Arty S7; I tried setting it up using the XADC IP in Vivado, and while I think I may have properly used the signals the IP has instantiated for me, I'm just a little confused which pins to connect the analog inputs to. To be more specific, the IP created two signals "vauxp0" and "vauxn0" which I think are the analog inputs: vauxp0 => Vaux0_v_p, vauxn0 => Vaux0_v_n, I suspect these need to be connected to analog input header pins on the Arty S7, and I found two pins called "Vaux0_v_p" and "Vaux0_v_n" in the .xdc constraint file which I connected to the signals above: ## ChipKit Single Ended Analog Inputs ## NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). ## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { Vaux0_v_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { Vaux0_v_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] My questions were: 1) Have I connected the IP-generated input signals to the right pins from the .xdc file? 2) If so, which header pins are these on the Arty S7 board? That is, where in the board should I connect my external analog signal to? Thank you all very much!
  7. srath22

    PULPino on Arty-7 35T

    We are new and we are trying to implement pulpino on Arty-A7 35t FPGA board. Can any one suggest a proper flow from generation of RTL to application development ? We are using Vivado 2015.1 . Please help us to get it right. Thank You
  8. srath22

    Arty-A7 35T IPS

    We are looking for Arty-A7 35t board IPs. Can anyone suggest where to get those files ?
  9. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start). The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance. design_1.bd
  10. Hello, I checked the tutorials and read the pdf-s on the AXI Interrupt controller. However, i could use come clarification about a couple of things. In Microblaze advanced configuration there's an option to set interrupts to NONE/NORMAL/FAST, or leave it in AUTO mode. Is this setting linked to the AXI interrupt controller creation process? I mean if it run Block Automation, and enable Interrupt Controller, then AXI Interrupt Controller IP is created, but the setting doesn't change in the microblaze settings (for example it stays AUTO/NONE). Does that mean if i want a normal mode interrup controller setup, then i have to set it to normal in the AXI Interrupt Controller, also in the microblaze settings? What are the differences between FAST and NORMAL mode? Docu states: "In this mode, AXI INTC provides the interrupt vector address using the interrupt_address signal, and the processor acknowledges an interrupt through the processor_ack signal." Does that mean that if i have it in NORMAL mode, then it will not send the vector to the processor, and those lines doesn't need to be connected? Does the Interrupt interface on the microblaze and the AXI Interrupt Controller have to be connected in both NORMAL and FAST mode? If not, they communicate over AXI? If i have a timer that is the only interrupt source in my design, and i want a callback function to be called every time the timer sends an interrupt, how can i implement this with the simplest AXI INTC? Can i do this in normal mode?
  11. Hello. I believe similar questions are present on the forum before mine. But I specifically want to know aside from the peripherals difference (RAM, SDCard, VGA etc.), is it ideal to assume the HDL designs (except the peripherals IP) would be compatible with both of them if one is supported by some project. For instance, lowRISC has a guide based on Nexys for its core booting Linux (https://www.lowrisc.org/docs/untether-v0.2/fpga-demo) whereas SiFive E310 has been demonstrated on Arty. The LiteX project supports both the boards (at least from the code base it looks so). Can someone experienced with this please guide me. I'm inclined towards the Nexys version as most of the peripherals I would be interested in are present on board, but I certainly don't want to have limited capabilities for certain projects compared to Arty. Thanks
  12. Hi, I've got my Arty sending out UDP packets to my laptop, without any soft CPU involvement. I've still got to add checksums and so on, but at least it works! http://hamsterworks.co.nz/mediawiki/index.php/ArtyEthernet
  13. I am working with an Arty design and I have noticed that while I have no intra-clock timing failures, I still have high severity warnings in the "check timing" portion of my timing summary related to not having constraints for input and output delay (no_input_delay and no_output_delay). Does digilent provide suggested timings for the on-board peripherals (like Ethernet and flash), or do I have to go through all the datasheets myself and estimate the trace delay? I found this thread from 2017, but the question was never resolved.
  14. Hello, I am working through some of the examples for the Arty A7 device. The device seems to come pre-loaded with firmware, some simple reference design that makes use of UART, LED's and pushbuttons. Is there some project I can download to reproduce this reference design? I am planning to overwrite this in the future, but I also wanted to have a copy. Thanks
  15. Hi, I have done a project for ARTY board which uses a bootloader to run my software application following this tutorial: How To Store Your SDK Project in SPI Flash My problem is that it works only after I press the PROG botton. So, after I connect the power, the FPGA PL get programmed (I see LED blinking correctly), but it seems that the bootloader does not. Only after I press PROG it does. What should I do to avoid pressing PROG at the beginning? Thanks, Lorenzo
  16. elAmericano

    Artix7 & ZedBoard

    Hello, My group has acquired the two boards Artix A7 and ZedBoard for developing some applications. I am noticing couple differences regarding projects and documentation. One such difference has to do with the reference base design. For Artix A7 I am finding the PMOD ports, and I2C, SPI, UART, Ethernet included in Board connections. For ZedBoard, very few peripherals are included in the base design I was able to locate. Question: For developing new applications for Zynq, can you provide some information regarding Zynq base desing. Is there more complete project for integrating HDMI / PMODS/ etc.. Does the Arty Z7 provide better support with respect to this feature? If so we may consider to develop on this board alternatively. I appreciate your feedback,
  17. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store a_width : integer := 6 -- width of the adress bus ); port ( i_clk : in std_logic ; btn : in std_logic; led : out std_logic; led_2 : out std_logic; test_io : out std_logic_vector ((d_width + a_width + 1) downto 0) ); end io_test; architecture Behavioral of io_test is signal clk_counter : integer := 0; signal clk_1hz : std_logic := '0'; signal test_io_buf : std_logic_vector((d_width + a_width + 1) downto 0) := "000000000000000000000001"; signal insr : std_logic_vector(2 downto 0); signal led_buf : std_logic := '0'; begin btn_async : process(i_clk) begin if(rising_edge(i_clk)) then insr <= insr(1 downto 0) & btn; end if; end process; io_test : process (i_clk) begin if(rising_edge(i_clk) and i_clk ='1') then if (insr(2 downto 1) = "01") then test_io_buf <= test_io_buf(d_width + a_width downto 0) & '0'; led_buf <= not led_buf; end if; end if; end process; test_io <= test_io_buf; led <= btn; led_2 <= led_buf; end Behavioral; If I simulate the file with: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity test_of_ram is end test_of_ram; architecture Behavioral of test_of_ram is component io_test port( i_clk : in std_logic ; btn : in std_logic; test_io : out std_logic_vector ((16 + 6 + 1) downto 0); led : out std_logic ); end component; ------------------------------------------------------------------------------ -- Signals and Types ------------------------------------------------------------------------------ constant OFFSET : integer := 15; signal btn, clk : std_logic := '1'; signal led : std_logic; signal test_io : std_logic_vector ((16 + 6 + 1) downto 0); begin dev_to_test: io_test port map( btn => btn, test_io => test_io, i_clk => clk, led => led ); ------------------------------------------------------------------------------ -- Clock Stimulus ------------------------------------------------------------------------------ clk_stim : process begin wait for 5 ns; clk <= not clk; end process ; -- clk_stim ------------------------------------------------------------------------------ -- IO Stimulus ------------------------------------------------------------------------------ io : process variable cnt: integer := 0; begin for I in 1 to 16 loop wait for 100ns; btn <= not btn; end loop; end process ; -- read_write_stim end Behavioral; I get the following result: Which is exactly what I want. But led_2 never lights up and only gpio0 stays on 3.3V (measured with multimeter) xdc file: ## LEDs set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports led] set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports led_2 ]; #IO_25_35 Sch=led[5] #set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] #set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] ## Buttons set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L6N_T0_VREF_16 Sch=btn[0] #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] ## Clock signal set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports i_clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk] #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## ChipKit Outer Digital Header set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {test_io[0]}] set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {test_io[1]}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {test_io[2]}] set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {test_io[3]}] set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {test_io[4]}] set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {test_io[5]}] set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {test_io[6]}] set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { test_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {test_io[8]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {test_io[9]}] set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {test_io[10]}] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {test_io[11]}] set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {test_io[12]}] set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {test_io[13]}] ## ChipKit Inner Digital Header set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {test_io[14]}] set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {test_io[15]}] set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {test_io[16]}] #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ram_addr[1] }]; #IO_25_14 Sch=ck_io[29] set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports {test_io[17]}] set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {test_io[18]}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {test_io[19]}] set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {test_io[20]}] #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { test_io[21] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { test_io[22] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports test_io[21]] #set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {test_io[7]}] set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {test_io[22]}] set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {test_io[23]}] #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
  18. I have the Arty A7-100T and have successfully built and run a project using the PMOD RTCC module, which uses the I2C interface. I modified the project to use the I2C pins on connector J3 of the Arty and enabled the pullup resistors. I wired the SCL & SDA pins to the PMOD RTCC and all is good. It runs the same as if connected to the PMOD connector. So now I am trying to build my project without using the I2C defined port that is in the board definition files. I want to connect directly to the 6 control and data lines that make up the I2C port on the AXI IIC IP and I want to be able to use any of the available I/O pins on the board for SCL & SDA (I realize that I will need external pullup resistors unless the internal pullups available in the FPGA are sufficient). The problem I am having is that I get failures during synthesis that seem to not like me trying to use bi-directional tristate pins for SCL and SDA. I have a Verilog file that I am using for the bi-directional tristate control: module tristate(IO_Data, Tx_Data, Rx_Data, Tri_En); inout IO_Data; // bidirectional data line input Tx_Data; output Rx_Data; input Tri_En; assign IO_Data = Tri_En? 1'bz:Tx_Data; assign Rx_Data = IO_Data; endmodule This is what it looks like wired up: These are the constraints on the 2 pins: set_property PACKAGE_PIN L18 [get_ports scl] set_property IOSTANDARD LVCMOS33 [get_ports scl] set_property PACKAGE_PIN M18 [get_ports sda] set_property IOSTANDARD LVCMOS33 [get_ports sda] This is the type of error I get: [Designutils 20-1595] In entity system_tristate_0_1, connectivity of net IO_Data cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: inout IO_Data Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal. My questions are: 1) Should I be able to connect I2C in this manner without having the port defined in a board definition file? 2) If so, any suggestions to correct my design or how to eliminate the errors I'm seeing? 3) Is there a tristate buffer primitive or IP that I should be able to use here (I cannot find one, which is why I attempted to create my own here)? 4) The PMOD RTCC module does not have pullup resistors on SCL & SDA. When using it with the PMOD connector and the board definition files it works. Are the internal FPGA pullup resistors enabled somewhere? I could not find that anywhere in the PMOD definition files or the Arty board definition files.
  19. Hello, I have combed through the forums but still have not found the answer I am looking for. I have the Arty board and Vivado 2015.4. I can create a project and I can select the Arty board in that process. I create a Block diagram on which to start building my 'circuit'. At this point I try two different ways to get a pmod port on the board: I click on the 'Board' tab and I find all the input and output ports (led, led_rgb, buttons, switches, spi, etc and Connector JA thu JD). I try and bring a JA onto the block diagram and get a message "Conn JA board component cannot be connected because no possible options to connect". Second thing I try is to click on 'Add IP' and select AXI_GPIO. Double click that and have the option to re-customize this block. Under 'Board Interface' is a drop down menu with , again, all the input/output items on the Arty board, but no pmod ports. I have tried this with and without bringing in the latest constraints file (from Github) with the same negative results. What does it take to get the pmod ports (Connectors JA-JD) on the block diagram? Switches and buttons and leds do move to the Block Diagram and they create an AXI block when they do. So what am I missing? Thank you for your time and help.
  20. i wanted to interface multiple digital serialiser with arty A7 35T board through pmod pins. And transmit the same data through UART. help me with the verilog code and other resource.
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