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Found 20 results

  1. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  2. I've been trying all day to pass HDMI through my Arty Z7 20 board, with almost no success. This is my block design: DVI to RGBI TMDS clock range is >=120MHz (1920x1080 preferred) RGB to DVI TMDS clock is also >=120MHz. It doesn't really matter, I tried all clock setups. The clocking wizard is set to 125MHz input clock and 200MHz output. These are my constraints: ## Clock Signal set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set ## HDMI RX Signals set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA ## HDMI TX Signals set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P I tried passing my laptop HDMI output through the Arty board, and also a SNES mini console. The result is a mostly black screen that keeps turning off and on again. If it's on, the display is really distorted and the colors aren't correct: I know that my device is working because with the demo that's installed in QSPI pass through is working. I've been trying different things all day long and now I'm really out of ideas what the problem could be. The monitors that I tried it with all support 60Hz. I also tried removing the reset signal or putting it on a button. I am honestly out of ideas. Next stop for me would be to start reading the DVI to RGB sources and I'd really like to avoid that. :) Please can anybody help me?
  3. Hello, according to the image from GenesysZu-3eg, I can see a HDMI Tx and Rx interface. Can I solder a tx and Rx HDMI port according to the schematic and use this connection? Can I have this support from Digilent? Is there any established circuit connection or just the design? Since it is not sure when 5ev will release, this kind of support will be really helpful.
  4. Hi, I've written a simple vhdl core to act as an EDID emulator. It's basically a PLB Master core, catching interrupts from a PLB Slave XPS_IIC core attached to HDMI SDA/SCL line to manage I2C/DDC protocole. This core works fine when xps_iic is connected to J3:IN I2C ports (M16 for SCL, M18 for SDA). However, nothing happens when the xps_iic is connected to J1:IN I2C ports (C13 for SCL, A13 for SDA). I guess I'm missing something with JP2 and JP4 jumpers. Can you please tell me the correct jumper settings to have J1:IN hdmi port act the same way as J3:IN ? Please note that I need for my project to have both J1:IN and J3:IN work together as I'm working with 2 video streams. Thank you for your help.
  5. I'm following along with the instruction provided on the GitHub ( to test the functionality of the Zybo board's HDMI ports. I followed the instruction to the T but cannot seem to get a signal to pass through. At first, I connected my cable box to the HDMI Rx and then I switched to my laptop. In both instances, not only did my TV monitor not detect a signal, but the output on the sdk terminal was that the HDMI-in was unplugged (see first attached photo). The HDP / LD9 LED near the HDMI port turns on, telling me it is detecting a signal. Using the Zybo-Z7 reference manual, I deduced that it might be due to an issue with resolution, but if I try to change the resolution, I get 'stuck' in that menu (see second attached photo) and have to restart the processes by clicking run-as -> Launch on Hardware. I also notice the clock frequency is set to 0, but I'm not exactly sure what could be the issue. I have also attached the block design and xdc file as I'm assuming the issue could be there since the pixel clock isn't running. design_1.pdf Zybo-Z7-Master.xdc
  6. I'm trying to use the hdmi output of my zybo z7-20 with pure HDL. I start with a very simple design which fills the screen with green (or so I intended). The design is as simple as connecting 3 IP cores: clocking wizard, video time controller and digilent's rgb2dvi. However, when I connect the board to a monitor, the monitor does not recognise a valid signal. I tried the HDMI demo and it worked so it is not a hardware issue. What am I doing wrong here?
  7. I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me. Any help would be appreciated. This is the 3rd or 4th tutorial/example I have tried since getting the board today. All in all everything has gone smoothly up to this point, but I have not the fpga/vivado experience to determine the issue. also my log output from vivado is attached. implementation.txt
  8. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[1]}] set_property -dict {PACKAGE_PIN L18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[1]}] set_property -dict {PACKAGE_PIN M14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[0]}] set_property -dict {PACKAGE_PIN N14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[0]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[2]}] set_property -dict {PACKAGE_PIN M17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[2]}] set_property -dict {PACKAGE_PIN M18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[3]}] set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[3]}] This works great on S7. The problem comes in when trying to use my HDMI PMOD with my new Arty A7 board. I looked up the PMOD pins, and got // for the A7: // top row is D12, A11, B11, G13 // bot row is K16, A18, B18, D13 // so TMDS1 is {B11, G13} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {D12, A11} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {B18, D13} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {K16, A18} = {hdmi_out_n[3], hdmi_out_p[3]} and my constraints look like this set_property -dict { PACKAGE_PIN G13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[1] }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[1] }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[0] }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[0] }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[2] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[2] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[3] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[3] }]; #IO_25_15 Sch=ja[10] So as far as I can tell, I made sure that the same JA pins map to what the HDMI PMOD expects. All the RTL code is the same. But now I get these errors Not sure if this is one error causing another, or two different errors. First of all, it seems like the PMOD negative and positive pins are somehow swapped. Or at least that's how I am interpreting ”the positive port (P-side) of a differential pair cannot be placed on a negative package pin”. The other mystery is site IOB_X0Y149 not being part of a differential pair. Any help is appreciated, since this is my first foray into worrying about pin polarity
  9. Hi, I want to create a test pattern generator project that uses the TPG IP to display the test patterns on the monitor via HDMI. For this I have been referring the Xilinx Video Series 19, however, the hardware used in the video is ZC702 and the hardware I am using is Zybo Z7-10. I also checked the HDMI demo available for Zybo Z7-10 but it does not include the TPG IP. Kindly suggest how can I achieve the same. I tried to replicate the block design from the video series 19 and made a few changes but I am not sure about it and got a few errors. I have attached the block diagram image and also the list of errors received. Thanks
  10. I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCC Receive the TMDS signals De-serialize them into 10-bit symbols Align the symbols using bitslips Tune the input delays for best reception Convert the TMDS symbols into data values Extract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs) Extract Video Infoframes from the ADP data Extract Audio Samples from the ADP data. Extract Raw Pixels from the VDPs Perform 422 to 444 conversion, if required by video format Perform YCbCr to RGB conversion, if required by video format Convert Studio Level RGB to Full Range RGB, if required by video format Convert Audio smaples to a relative db level Overlay Audio level meters over the video stream Convert the video stream and sync signals back to TMDS symbols Serialize them through a 10:1 serialisers Transmit the TMDS. I think that this is an awesome base for any video experimentation. I've even got to the trouble of making a GitHub repo for it: Please feel free to fork and extend.
  11. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory? If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking. If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed? Thanks in advance.
  12. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  13. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! ? Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Question 2 (pending): The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant. Some receivers get along with this signal but some unfortunately don't. To get a "true" 720p signal, pixel clock should be 74.25 MHz. Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ? Thank you very much for your help
  14. Tom G

    Genesys 2 HDMI demo

    Does anyone have the Digilent HDMI demo running on the most recent Xilinx IP cores / Vivado 2019.2? Upgrading the IP cores (necessary because I don't have a license to the old ones) seems to result in the bitstream generation failing and a ton of error messages that I can't see how to resolve. Any help much appreciated.
  15. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  16. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  17. Does the demo design ( support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  18. birca123


    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, Toni Birka
  19. Hello, Is there any way that I can connect the Nexys4DDR to an HDMI connector, for example using a breakout board such as this one The critical factor would be getting access to 4 differential pair outputs (TMDS) from the Artix-7 FPGA. I note that there is no HDMI PMOD available, which suggests that these pins are actually not available externally on this board. I already have the Nexys4DDR, which is the right board for me. I don't need the dedicated Nexys Video, I'm just trying to upgrade my display output from VGA to HDMI - which could be a relatively simple job. Related to this, if I can post my request for the next version of the Nexys4 board: replace the VGA connector with a DVI connector and connect both the "VGA" pins and the "HDMI" pins from the DVI connector to the FPGA. Users can then either uses a DVI/HDMI cable or an DVI/VGA adaptor at preference.
  20. From the album: - Firmware for capturing HDMI and DisplayPort via USB and Ethernet

    __ _____ __ _______ ___ __ _________ / // / _ \/ |/ / _/ |_ | / / / / __/ _ ) / _ / // / /|_/ // / / __/ / /_/ /\ \/ _ | /_//_/____/_/ /_/___/ /____/ \____/___/____/ alternative Copyright 2015 / EnjoyDigital Alternative HDMI2USB gateware and firmware based on Migen/MiSoC [> Supported Boards ------------------ This firmware is supported on the following to boards; * Digilent Atlys - The original board used for HDMI2USB prototyping. Use `BOARD=atlys` with this board. * Numato Opsis The first production board made in conjunction with project. Use `BOARD=opsis` with this board.

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