Jump to content

Search the Community

Showing results for tags 'xadc'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 13 results

  1. memo

    Arty S7 XADC Pins

    Hi there, I hope everyone is safe and doing well, and thank you checking out my forum post; I would greatly appreciate your help :D I was trying to get the XADC working on the Arty S7; I tried setting it up using the XADC IP in Vivado, and while I think I may have properly used the signals the IP has instantiated for me, I'm just a little confused which pins to connect the analog inputs to. To be more specific, the IP created two signals "vauxp0" and "vauxn0" which I think are the analog inputs: vauxp0 => Vaux0_v_p, vauxn0 => Vaux0_v_n, I suspect these need to be connected to analog input header pins on the Arty S7, and I found two pins called "Vaux0_v_p" and "Vaux0_v_n" in the .xdc constraint file which I connected to the signals above: ## ChipKit Single Ended Analog Inputs ## NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). ## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { Vaux0_v_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { Vaux0_v_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] My questions were: 1) Have I connected the IP-generated input signals to the right pins from the .xdc file? 2) If so, which header pins are these on the Arty S7 board? That is, where in the board should I connect my external analog signal to? Thank you all very much!
  2. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  3. For my project, I was asked to use the xadc portion of the zybo board to read the data from the DFRobot Gravity Analog Electrical Conductivity (EC) Sensor. The link of the sensor is here: https://www.dfrobot.com/product-1123.html Just to give a summary on this product, it has the supply voltage of 3V to 5V and output voltage of 0V to 3.4V. I have asked this question before, maybe due to the unclarity of the question, nobody has answered me. The link is here: I have been trying to learn the basics of xadc and attempted some project. I created one project which allows me to read the data from ZYBO's internal temperature, voltage and the external analog input source (if that is correct) The block design, the code, the zipped vitis file and the outcome are below. Additionally, I have tried the sensor in my Arduino. The detail will be shown below as well. Here are some areas of concern. 1) I knew that for zybo xadc, it only supports the supple voltage up to 1V ONLY but my sensor output voltage can go up to 3.4V. I am worried if I straightly connect my analog input of the sensor into the zybo xadc output at port A. The Zybo Board may be damaged. So is there a way to minimise the output voltage so that the analog input can successfully insert into the zybo without damaging the board. I am thinking of using 2.2K ohm and 4.7K ohm resistor in series to solve the issue but I am not certain about that. 2) If the zybo can configure the DF Robot Gravity EC sensor smoothly through using resistors or other means, how can I ensure the result is accurate? Also, how should I transfer my code in Arduino into the Vitis Code. Do I need to change my Arduino code by a lot in order to allow the Vitis to understand. Thanks in advance helloworld1029 xadc_code (1).txt Electrical Conductivity Code For Arduino.txt workspace_sensor.zip
  4. I want to see the digitalized output with sine wave analog input using xadc wizard. But I am not obtaining sine wave output instead I get a constant output. I have attached the image of the simulation output. The design.txt file is the analog stimulus file stored as example file in xadc. xtest_tb: `timescale 1ns / 1ps module xtest_tb; wire [15 : 0] di_in; wire [6 : 0] daddr_in; wire den_in; wire dwe_in; wire drdy_out; wire [15 : 0] do_out; reg dclk_in; reg reset_in; wire vp_in; wire vn_in; wire [4 : 0] channel_out; wire eoc_out; wire alarm_out; wire eos_out; wire busy_out; initial begin dclk_in=1'b0; forever #5 dclk_in=~dclk_in; end initial begin reset_in=1'b1; #200 reset_in=1'b0; end x_test DUT ( .di_in(16'b0), // input wire [15 : 0] di_in .daddr_in({{2{1'b0}},channel_out}), // input wire [6 : 0] daddr_in .den_in(eoc_out), // input wire den_in .dwe_in(1'b0), .drdy_out(drdy_out), // output wire drdy_out .do_out(do_out), // output wire [15 : 0] do_out .dclk_in(dclk_in), // input wire dclk_in .reset_in(reset_in), // input wire reset_in .vp_in(), // input wire vp_in .vn_in(), // input wire vn_in .channel_out(channel_out), // output wire [4 : 0] channel_out .eoc_out(eoc_out), // output wire eoc_out .alarm_out(alarm_out), // output wire alarm_out .eos_out(eos_out), // output wire eos_out .busy_out(busy_out) // output wire busy_out ); endmodule
  5. Good Afternoon Sir/Madam, I am trying to display the internal temperature of my device on a four 7-segments anodes hexadecimally. In my attached archive, I have already instantiated the XADC. After going over the user manual of 7 Series FPGAs and Zynq-7000 SoC XADC, Here is what I already know: I am aware that the measured temperature value is in address 00h. I am aware that channels 4 to 0 need to be all zeros to measure the on chip temperature. I am aware that the first 64 access locations (DADDR[6:0] = 00h to 3Fh) of DRP are read only which contain the ADC measurement data. Here is what I don't understand: -Why am I getting zeros from the output of Dynamic Reconfiguration Port (DRP)? For your information, I am programming in VHDL on Vivado 2020.1. Kind regards, ElectronicEngineer Temperature_start.xpr.zip
  6. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling rate. If I am not wrong the FFT resolution should be 961.54*10^3/4096 (for a 4096 point FFT). Backtracking from the scope, it appears that there is an offset from the expected sampling rate. Example: While 23.5 KHz is expected to fall in the 100th bin it falls in 111th bin. The sampling rate (computed from the FFT resolution formula - observing output) would be around 870 KSPS. Question 2) Would the sampling rate change if I use a 50 MHz DCLK clock instead of 100 MHz? The IP core indicates that the actual sampling rate would be 961.54 KSPS (same as that with 100 MHz clock) but I observed a shift in FFT output yet again. This time the sampling rate (computed from the FFT resolution formula) falls around 835 KSPS. Please help! P.S. - In my design I used a AXI-4 stream register slice as a pipeline stage to account for latency involved in multiplication and addition operations on the FFT output so that the signals from xfft_0 appear at the same time as the data. Frames are sent at the same rate (100MHz) at which the FFT is operated => BRAM read frequency = FFT CLK = 100 MHz. 3) Question on FFT: My FFT output appears to be almost as expected (except for the constant offset in frequency bins). After every 4095th bin there is a repetition of bin value 4080, (for a certain interval, until next 0) and I with a peak at this value. I do not understand the reason behind this. Please provide some insight on this as well.
  7. Hi there, I have been not having luck in reading the aux pins on the zybo z7 board. I have setup the system as below: The XADC is setup with DRP and channel sequencer in continuous mode, with the setup as below: I can read the voltages on the XADC system monitor dashboard as below: But the XADC only read 0x5999 on Aux 15 Pin, as seen below: As you will see above, Aux 6 and Aux 14 is stuck at 0x5999 and Aux 7 and Aux 15 is fixed at 0x5111. I don't get any errors only a critical warning: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. I have been debugging this for two days now and I am unable to fix this issue. So any help to get the analog inputs on aux pins converted is greatly appreciated! Cheers, Gautam.
  8. Hello, Merry Christmas hope you guys are doing great. I am a beginner in digital design course and i want to implement this xadc demo project from digilentinc reference on my Basys3 FPGA. I'm having problems on the step 4 which is running the project as i can't figure the physical connections to connect to the JAXDC port on FPGA. Can someone confirm if the connections i have done in this picture are right? One last question. When you open the XADC Basys3 Demo project and see its constraints, only package pins i don't understand are these A12,B13 ones. Where are they located on FPGA? I'm assuming there are some internal connections like seven segment decoder have. Any help appreciated. Thank You. Regards, Zain
  9. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? and also 3. How sensible are the XADC-Ports really? How high do currents and/or voltages have to be to cause damages? Are maybe the only important rules to prevent short circuits through XADC-hardware by placing a preresistor and prevent voltages above 3.3V? Thank you! /edit Question #4 Would a combination of resistors (one would be enough I think) and Zener-diodes (breakdown at 1V), as you can see below, securely protect any hardware onboard of any mistakes done outside XADC-Pmod? This is just a result of my tiny little knowledge of analog elecronics. Simulation does agree but that is just simulation. Maybe in reality and for a very short time there still could be constellations causing voltages and/or currents that could damage my board... Or is this schematic below really a secure protection? Depending on how XADC-hardware looks inside, theoretically a short circuit current would cause high voltages which should also be taken by the diodes, ...I guess. So are resistors maybe not even needed and only Zener-diodes would already give a safe protection of hardware damages?
  10. Hello, I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets". Design is below: As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. Pin assignment are as under for VC707 Schematics diagram for VC707 Any help will be appreciated. Thanks,
  11. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design (https://github.com/Digilent/Zybo-Z7-20-base-linux) with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  12. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect Pmod DA3 clock to XADC clock creating a unique clock for the entire design. This design was validated. Creating a HDL Wrapper, it has a correct synthesis, implemetation and bitstream. Programing the board i dont get any analog value for output Pmod DA3, it only works output LED[15:0]. Modules works correctly independently. Should i make a different connection for clocks? I dont know if there is a clock problem or other type problem. i attach the project Can anyone help me? Thanks! XADC + DA3.rar
  13. Hello, I have a Zybo Board (Version 1 Rev. and I have a strange Issue with my XADC which samples the input for the channel AD7 on the channel AD14. Please take a look at my setup. I want to use the differential Channelpair 7 and 15 (like in the Photo - upper row VIn and lower row ground from my voltage source). My software gives me the results for channel 14 and 15 and the value for channel 7 stays constant even when I increase or decrease the input voltage. Only channel 14 and 15 change her values. I expect that channel 14 stays constant and channel 7 change his value. Temperature: 46.1576 Degree Celsius Vcc INT: 0.9961 V Vref+: 1.25 V Vref-: 3.00 V Channel 7: 2351 Channel 14: 26032 Channel 15: 32767 My code looks like this #include "stdio.h" #include "xparameters.h" #include "xadcps.h" XAdcPs XAdc; XAdcPs_Config* ConfigPtr; int main() { ConfigPtr = XAdcPs_LookupConfig(XPAR_XADC_DEVICE_ID); if(ConfigPtr == NULL) { xil_printf("Invalid XADC configuration!"); return XST_FAILURE; } XAdcPs_CfgInitialize(&XAdc, ConfigPtr, ConfigPtr->BaseAddress); if(XAdcPs_SelfTest(&XAdc) != XST_SUCCESS) { xil_printf("Self test failed!"); return XST_FAILURE; } XAdcPs_Reset(&XAdc); XAdcPs_SetSeqChEnables(&XAdc, XADCPS_SEQ_CH_AUX07 | XADCPS_SEQ_CH_AUX14 | XADCPS_SEQ_CH_AUX15); XAdcPs_SetSequencerMode(&XAdc, XADCPS_SEQ_MODE_CONTINPASS); xil_printf("Start...\n\r"); while(1) { u32 Temp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_TEMP); printf("Temperature: %.4f Degree Celsius\n\r", XAdcPs_RawToTemperature(Temp)); u32 VCCInt = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VCCINT); printf("Vcc INT: %.4f V\n\r", XAdcPs_RawToVoltage(VCCInt)); u32 VREFp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFP); printf("Vref+: %.2f V\n\r", XAdcPs_RawToVoltage(VREFp)); u32 VREFn = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFN); printf("Vref-: %.2f V\n\r", XAdcPs_RawToVoltage(VREFn)); u32 Ch7 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MIN + 7); xil_printf("Channel 7: %lu\n\r", Ch7); u32 Ch14 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX - 1); xil_printf("Channel 14: %lu\n\r", Ch14); u32 Ch15 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX); xil_printf("Channel 15: %lu\n\r", Ch15); xil_printf("-------------\n\r"); for(u32 i = 0x00; i < 0xFFFFFF; i++); } return XST_SUCCESS; } With the following XDC file: ##Pmod Header JA (XADC) set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_p] set_property PACKAGE_PIN N16 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_p] So what is going wrong here?
×
×
  • Create New...