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Found 19 results

  1. Hello I just started working with FPGA, forgive my ignorance. I've been trying to run the project over this link for a few days now -> https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi. I am using Vivado 2019.1, I download 2018.2-2 version and Vivado has automatically updated the 2018.2 version in the link. After downloading, I program my ZYBO Z7 card without making any changes by following the steps in the README section many times. My connections are as follows: Laptop HDMI out -> Zybo Z7 HDMI RX, Zybo Z7 HDMI TX -> HDMI to VGA cable -> Monitor VGA input. When I click Run System Debugger, the FPGA connection is broken and the UART interface does not work while the connections are this way. When I disconnect the HDMI RX (that is, disconnect the Laptop from the HDMI), these images come to the monitor, and the UART interface works. Then I used an HDMI TV instead of a VGA monitor, and although the FPGA connection was not broken this time, the UART interface did not work (it does not type anything into the terminal when I press the keyboard), and the Laptop screen was not transferred to the TV. I set the laptop resolution to 1280x720 and more different resolutions. Nothing can be changed. While my board is connected to the TV and laptop, the HDP led next to the HDMI RX is on, I think the laptop is transferring images to the board, but I'm starting to think that there's a problem with transferring images from the board to the HDMI TX. I can say that I have studied all the Zybo Z7-10 pass-through errors on the forums, but I have not been able to find a solution. I hope I was able to explain my problem. Can you help me? Or some information about how to transfer the image from the laptop to the monitor via FPGA? Thanks.
  2. Hi there! I'm an electrical engineering student and my group has been thrown in cold water: We have to do an SPI Project where we connect a PMOD-Mic3 to our Basys3 Board and measure the frequencies of sounds by giving the Mic signal out to the onboard LEDs. A lot of LEDs have to light up when the frequency is high (over 500 Hz) and less when the frequency gets lower. [We have to create a Vivado VHDL Project.] We have huge problems understanding the core of the exercise. So far, after hours of research, we were not succesful with anything but especially: Establishing SPI-Communication (Master-Slave) Creating working shift-registers Our question is: has anyone done anything like that and can provide us with tipps/tricks or even a working examplary code? We value copyright and would never copy your work, we just need an idea as we have never dealt with FPGAs, VHDL or SPI before. We would appreciate every answer, thank you all a lot in advance! Your ElectricalEngStudent :)
  3. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port( clk : in std_logic; rst : in std_logic; start : in std_logic; input : in std_logic_vector(7 downto 0); done : out std_logic; output : out std_logic; showstates: out std_logic_vector(3 downto 0) ); end entity; architecture dataflow of rs232_omo is type states is (idle_state,start_state,send_state,stop_state); signal present_state,next_state : states; signal data,data_next : std_logic; begin process(clk,rst) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin if rst='1' then present_state<=idle_state; count:=0; data<='1'; elsif rising_edge(clk) then present_state<=next_state; count:=count+1; index:=index+1; data<=data_next; end if; end process; process(present_state,data,clk,rst,start) variable count : integer range 0 to clk_max; variable index : integer range 0 to 10; begin done<='0'; data_next<='1'; case present_state is when idle_state => showstates<="1000"; data_next<='1'; if start='1' and rst='0' then count:=count+1; if count=clk_max then next_state<=start_state; count:=0; end if; end if; when start_state => showstates<="0100"; data_next<='0'; count:=count+1; if count=clk_max then next_state<=send_state; count:=0; end if; when send_state => showstates<="0010"; count:=count+1; data_next<=input(index); if count=clk_max then if index=7 then index:=0; next_state<=stop_state; else index:=index+1; end if; count:=0; end if; when stop_state => showstates<="0001"; count:=count+1; if count=clk_max then next_state<=idle_state; done<='1'; count:=0; end if; end case; end process; output<=data; end architecture; Constraints: set_property PACKAGE_PIN V17 [get_ports {input[0]}] set_property PACKAGE_PIN V16 [get_ports {input[1]}] set_property PACKAGE_PIN W16 [get_ports {input[2]}] set_property PACKAGE_PIN W17 [get_ports {input[3]}] set_property PACKAGE_PIN W15 [get_ports {input[4]}] set_property PACKAGE_PIN V15 [get_ports {input[5]}] set_property PACKAGE_PIN V14 [get_ports {input[6]}] set_property PACKAGE_PIN W13 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {input[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {showstates[0]}] set_property PACKAGE_PIN L1 [get_ports {showstates[3]}] set_property PACKAGE_PIN P1 [get_ports {showstates[2]}] set_property PACKAGE_PIN N3 [get_ports {showstates[1]}] set_property PACKAGE_PIN P3 [get_ports {showstates[0]}] set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN R2 [get_ports rst] set_property PACKAGE_PIN T1 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports done] set_property IOSTANDARD LVCMOS33 [get_ports output] set_property PACKAGE_PIN V3 [get_ports done] set_property PACKAGE_PIN V13 [get_ports output] My testbench simulation got attached. And on-board, apparently I stuck with 'idle_state'. For any kind of help, I thank y'all in advance.
  4. Hi, I am having a problem in programming my FPGA. There was no problem in synthesis, implementation and generating bitstream. However, I got these errors: "[Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. [Labtools 27-3165] End of startup status: LOW". After generating .bin file instead of .bit file, I got rid of the first error [Labtools 27-3303]. However, I stil cannot program the FPGA because of the second error [Labtools 27-3165]. I have tried different versions of vivado, different BASYS3 FPGAs, different computers, and cables, but I can't solve it. I don't get these errors in my other codes but only in designs using VGA port of the FPGA.
  5. sciaomi

    -

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  6. Hello eveyone, I am working on TLC5940 to drive LEDs with FPGA cyclone V DE10; Could any one here help me with a VHDL code to activate leds via FPGA? I would be so gratefull. Many thanks in advance
  7. I am in the proposal process that utilizes the Eclypse Z7 along with the Zmod ADC 1410. We are hoping to utilize vetted code to configure the ADC and accept the sample data. We need to do some processing and interfacing to external components so we cannot use the provided bit file. I have looked over GitHub repository (https://github.com/Digilent/Eclypse-Z7-HW) and couldn’t find any VHDL or Verilog files?
  8. Good Afternoon Sir/Madam, I am trying to display the internal temperature of my device on a four 7-segments anodes hexadecimally. In my attached archive, I have already instantiated the XADC. After going over the user manual of 7 Series FPGAs and Zynq-7000 SoC XADC, Here is what I already know: I am aware that the measured temperature value is in address 00h. I am aware that channels 4 to 0 need to be all zeros to measure the on chip temperature. I am aware that the first 64 access locations (DADDR[6:0] = 00h to 3Fh) of DRP are read only which contain the ADC measurement data. Here is what I don't understand: -Why am I getting zeros from the output of Dynamic Reconfiguration Port (DRP)? For your information, I am programming in VHDL on Vivado 2020.1. Kind regards, ElectronicEngineer Temperature_start.xpr.zip
  9. Hello everyone. I'm working on a project wtih my friend. To accomplish it, we need to get 12 bit data from microphone and observe the output on LEDs. We couldn't figure out what is wrong with the code...spi_master.vhd mic3_xdc.xdc mic3.vhd spi_master_cs.vhd
  10. Do you need a board to board data interface because you've run out of IO or need a high speed PC interface? Interested in learning about how to deal with multiple clock domains? Just want to learn VHDL or the HDL design source flow? Do you want to stream your Arty A7 with ADC PMOD samples to a PC but don't have a suitable interface? Keep reading... Here's a project to try out and study. Zygot revisits the differential PMOD to find a use for it. Is this a new Differential PMOD Challenge? There's only one way to find out. HighSpeedUartInf_Rev1.zip
  11. I think my question is general but i want to know how to initialize Pmod OledRGB using case when-statment i found some vhdl codes using this method but i cant understand it
  12. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  13. Hello everyone, I’m a newbie on working on zedboard, and I want to use my Zedboard to communicate with Pmod MIC3 this time. I did a few researches about how to use the Pmod MIC3, and I think I found something useful in another post, link: https://forum.digilentinc.com/topic/19342-driver-code-for-pmod-acl2-and-pmod-mic3/ I’m really appreciate and thanks for their help, but unfortunately I still have no idea of how to make my Pmod MIC3 to run with my Zedboard. I know Pmod MIC3 is using SPI communication protocol and I read what SPI is, link: https://reference.digilentinc.com/learn/fundamentals/communication-protocols/spi/start But I’m not sure is that Quad SPI is the same as SPI in Zedboard. About the Pmod MIC3, I know that it used a MEMS Mic and an ADC, but I also don’t know how to implement it, like do I need a code or IP cores to handle these 2 components? Here is a simply conclusion of my questions: 1. How to use SPI in Zedboard? (Any pin configuration is required?) 2. Do I need a code or something else to handle the ADC and MEMS Mic in Pmod MIC3? 3. Is it possible to make this project work in .vhdl? Or I need something else? 4. How to getting start with? 5. Importance of IP core I know IP cores is an important thing, but I don’t get a clear idea about it and how it works with Vivado. Any help and reference suggestions is appreciated! Thanks ? !!
  14. MoGamaal

    Display Variables

    I want to know how to display variables on PmodOLEDRGB from Sensors via artix-7 kit in vhdl
  15. Hi! I bought a Nexys 4 board and a Pmod OLED 128x32 screen, on which I am going to implement the Snake game, by programming the FPGA in VHDL. The problem that I encountered, is that I don't know how to set a pixel on the screen. I can only assume that I have to make some changes in the memory that maps the screen, something related to the example that I have found on the Pmod OLED's reference page, under the Example projects section. The given example takes a group of pixels and sends a character (its ASCII code), using the alphabet_screen variable, which is a memory. My question is, how should I write/ create the memory, in order for me to set only one pixel, not a group of them? Also, there is a charLib IP that is being used -- how can I export this from the example project, into my Snake project? Thank you!
  16. Hello, I new on Basys 3, and I need some examples for programming FPGA. In the resource center there are a lot of them, but the examples are written in verilog. I am using VHDL, so the questión is: Is there the same examples like the resource center written in VHDL?
  17. Hello! I have created some VHDL code (attached) to test if DA4 convertor works. The simulation reveals no problems with timing of SCLK, DATA and SYNC channels according to the AD5628 data sheet, however output of the eight out data pins of DA4 does not work. Basically I am trying to send the the data to JB PMOD. Command and address are tuned by the eight switches on the Nexys4. The used command is 0011 and the address is 1111 (is that correct, by the way?), but I have tried plenty of other commands. Still the problem persists — no out data from DA4. Please do not hesitate asking for additional information. Thank you for your help. pmod.vhd.txt
  18. Hello everybody, I want to implement a dac example into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input. Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you. port( -- Users to add ports here output : out std_logic := '0'; -- User ports ends ); -- Add user logic here -- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP. process(S_AXI_ACLK) variable index : integer := 0; variable counter: integer := 0; begin if rising_edge(S_AXI_ACLK) then case index is -- 4 Command Bits start when 0 => output <= '0'; when 1 => output <= '0'; when 2 => output <= '1'; when 3 => output <= '1'; -- 4 Command Bits end -- 4 Don't Care Bits start when 4 => output <= '0'; when 5 => output <= '0'; when 6 => output <= '0'; when 7 => output <= '0'; -- 4 Don't Care Bits end -- 16 Data Bits start when 8 => output <= slv_reg0(16); when 9 => output <= slv_reg0(17); when 10 => output <= slv_reg0(18); when 11 => output <= slv_reg0(19); when 12 => output <= slv_reg0(20); when 13 => output <= slv_reg0(21); when 14 => output <= slv_reg0(22); when 15 => output <= slv_reg0(23); when 16 => output <= slv_reg0(24); when 17 => output <= slv_reg0(25); when 18 => output <= slv_reg0(26); when 19 => output <= slv_reg0(27); when 20 => output <= slv_reg0(28); when 21 => output <= slv_reg0(29); when 22 => output <= slv_reg0(30); when 23 => output <= slv_reg0(31); -- Data Bits end when others => end case; if counter = 0 then index := (index + 1) mod 24; end if; counter:= ( counter +1) mod 20; end if; end process; -- User logic ends Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.
  19. I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, output reg HSync1, output reg VSync1 ); VHDL: component testoverlay_0 is port ( rst_n: in STD_LOGIC; clk: in STD_LOGIC; RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 ); HSync1: out STD_LOGIC; VSync1: out STD_LOGIC ); end component testoverlay_0; test_overlay: component testoverlay_0 port map ( rst_n => reset_1, clk => sys_clk_i_1, RGBOut(23 downto 0) => v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0), HSync1 => v_axi4s_vid_out_0_vid_io_out_HSYNC_1, VSync1 => v_axi4s_vid_out_0_vid_io_out_VSYNC_1 );
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