Search the Community

Showing results for tags 'jtag'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

  1. Hello, I'm trying to connect a JTAG-HS3 (Rev.A) with a Spartan-7 (XC7S6-1FTGB196C) using Vivado Lab Edition 2021.2 but Vivado keeps telling me that I should check cable connectivity and Spartan-7 cannot be found.I tried two HS3 to be sure it's not damaged. I tried speed down to 125kHz. A Xilinx platform cable USB II works fine with same cable (HS3 needs a extra pin header since HS3 and platform cable have different genders). VREF is at 3V3. TCK, TMS, TDI and TDO have all a 10k pull up. The levels of TCK and TDI look fine during startup (3V3) but drop down to 1V after a short while. Spartan-7's flash hasn't been written yet. Any idea what's wrong here? What pull ups/downs are needed by HS3? Thanks a lot for all your help in advance!
  2. I am interfacing between a USB IC (a FT2232H FTDI chip) and a EEPROM IC (a 93AA56BT). To make the FTDI chip recognizable by Xilinx tools I need licensed Digilent Serial Numbers. How can I get a licensed serial number file to enable a USB-JTAG FTDI interface? Are these licenses keyed specifically to your chips? How can I enable a JTAG-USB FTDI interface?
  3. Hi all, I'm looking for an IBIS model or some sort of simulation model for the JTAG-SMT2. Please let me know if there is one available or something that I can use/reference for my SI simulations. Thanks!
  4. I'm having trouble programming a XCKU060 with the JTAG-HS3. Occasionally it succeeds and programs correctly, maybe 1 in 10 tries, but mostly programming fails with "ERROR: [Labtools 27-3165] End of startup status: LOW" Using the Xilinx DLC9G JTAG adapter on the same board always succeeds in programming. Looking at a logic analyzer capture of the JTAG data there is a point where it looks like the TDI gets stuck high when the programming fails. It seems like there is some state or timing issue, but I'm not sure how to figure out what it is. I've tried different JTAG speeds, even down to 125Khz and it's always the same. Any help would be apricated. Thanks
  5. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  6. Chase

    JTAG-HS2 program issue

    Hi Digilent, I often got a information " The selected cable is being used by another application. Please retry the current operation. " from ISE iMPACT 14.7 when I used JTAG-HS2 device to program xilinx Spartan-6 device. But I did't use JTAG to do anything. I had make sure the driver is last. Does anyone have any idea? Thanks.
  7. Using a Genesys ZU board with a Xilinx FMC-105 board, I am attempting to connect a JTAG/TRACE probe using the JTAG header on the FMC. The probe reports TDO appears always high. I confirmed that the JTAG header on board (J28) works with a Xilinx probe, but does not work from the FMC. Examining the schematics I noticed that FMC_TDO is tied to JTAG_TDO and FPGA_TDI is tied to JTAG_TDI. That seems wrong to me. I was expecting that the FMC_TDO would go to the FTDI/USB TDI. I know the schematic page is omitted because of licensing issues, but can you confirm that the JTAG chain is functional from the FMC side.
  8. Hi everyone, so I have a atypical question about J17 port. So accidentally I damaged it, because the board fall and the micro usb cable was connected to PROG port so the board throws the port and causes a physical damage on it. I want to repair it, resoldering the port, because it’s more practical carry a Micro USB cable instead a JTAG to USB converter to program. So if you can help me with the verification of the connections. For example the USB OTG port J13 looks like all the pines are used although the UART port J14 looks like only uses 4/5 pines. I attach the photo of the crime scene and if someone could help me about the connections of the died points. Thanks a lot. ??
  9. I need to use the JTAG header to program the Zedboard, since the MicroUSB connector is physically damaged. I cannot find any documentation or forums about how to use the JTAG connector for programming the FPGA, so I am going to ask for your help. I have a basic design in Vivado for making switch 0 toggle led 0. The bitstream is ready to be sent to the FPGA. However, when I try to connect to the hardware, by clicking "Open target", it is unable to connect. When I try to manually connect: I am using Xilinx Platform Cable USB adapter for connecting the JTAG to the computer's USB input: I have the driver installed, and it appears in my list of devices when plugged in, and disappears if I unplug it, and is up-to-date: I suspect the jumpers may not be configured properly? But again I cannot find clear documentation on how to set this up. This is how mine is set up: Here is some information about my computer: I am using Vivado 2016.1, since that is used in a lot of the tutorials. I think the Diligent tutorial uses 2016.2. It also comes with the Zedboard board file, although I downloaded the one made by Diligent as instructed in the tutorial. I hope I have provided enough information. I appreciate any help!
  10. Hi , We are working on custom board based on zynq ultrascale+RFSOC . We had configured FTDI4232H channel 0 as JTAG port using FT_Prog utility. FPGA is not getting detected. It was found that specific EEPROM image has to be programmed for accessing FPGA through FTDI4232H. Can you please provide EEPROM image. If EEPROM image cannot be provided can we get preprogrammed FT4232H ICs. Thanks, sandeep
  11. Hello I have a Digilent USBJTAG HS2 and I'd really like to use it with TopJTAG's Probe software. The software has native support for the Digilent USB-JTAG but not the USB JTAG HS2. Having said that, it supports "custom" JTAG probes based on the FTDI chipset and recognises the HS2 as such. This is encouraging. When I select the Custom FTDI option it asks me to tell it what to do with the FTDI GPIOs and advises that different probed need their GPIOs setting up differently - often to enable buffers, drive tRST, and stuff like that. Sounds fair enough to me. The problem is that I cannot find documentation on how the GPIOs are used/configured on the HS2. The schematic would help, but the link to the schematic on the digilent website is dead. Can anyone help with the GPIO config or a schematic of the HS2? Many thanks. Andrew
  12. Hi, Managed to reprogram the JTAG-HS3 by accident, when it was connected together to the PC with another FTDI product that was meant to be reprogrammed. Vivado and Vitis does not recognize the cable anymore. Cannot find the original eeprom content anywere on the NET too. Could some one please help with this problem?
  13. Hi, We are using Metaware debugger with Digilent JTAG-HS2 cable Rev.A for JTAG connection. When 20 taps are in the chain, the chain is identified and we are able to connect to every processor and do single wr/rd, but failed to download data with some of the processors. In waves, we noticed that between successful write transactions we see an unexpected command of 4 clocks of high TMS with low TDI that coming from the driver. When reducing number of participating taps in the chain to 16, we are able to download to all remained processors successfully. The issue is consistent with other HS2-RevA cables. Issue sound similar to the following post in the forum: Is there any known HW issue in the cable or in the driver? Thanks.
  14. Hello everyone, I have been trying to interface JTAG HS3 + JTAG UART with Adalm-Pluto using Xilinx vitis. I have exported .XSA file for zynq zc010 and tried to build an standalone application for simple Hello World program, but I'm facing an error while i try to debug as lauch hardware. I faced the following error. Error while launching program: fpga configuration failed. DONE PIN is not HIGH
  15. I'm using Vivado v2020.2 (64-bit) with a newly purchased Arty S7. The Arty manual shows a schematic with USB (J10) connected to the JTAG interface of the FPGA and says "A PC can use the Digilent USB-JTAG circuitry (port J10) to program the FPGA any time the power is on" then goes on to say "The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J10) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J9." It sounds to me like only a USB cable is required and, if that's the case, I'm confused as to why the JTAG-HS2 cable would be needed. Con someone confirm I need only a USB cable and clarify what all the JTAG devices listed for sale in the Digilent store are used for?
  16. HI , i faced an issue to program the FPGA to my Spartan 3E board. WARNING:iMPACT:923 - Can not find cable, check cable setup ! My setup is using VM(Win7) with ISE 14.7 installed on my Win 10 PC. im using JTAG cable to program the FPGA, i try to download the Digilent Plugin Tool from here https://store.digilentinc.com/digilent-plugin-for-xilinx-tools-download-only/ but no response... can any one share me the ZIP files? or the files is corrupted ?
  17. My Basys3 board is not recognized in Vivado. I installed Vivido v2020.2 with little effort (although it took well over an hour). When I connect the USB cable and turn the power on nothing happens inside of Vivido. My board is jumpered for JTAG using JP1 (center pins). If I view the hardware manager it shows "unconnected No hardware target open". Clicking Open target than auto-connect shows no change. Only localhost (0) connected is listed. In Windows10 device manager, I do see 2 USB entries labeled "Digilent USB Device" with a value of, Dual RS232-HS (interface 0) and Dual RS232-HS (interface 1). I have power cycled my computer but no change. I can successfully copy the Project.BIT file to a USB drive and load the board that way after changing the jump. What do I try next to establish JTAG connection?
  18. Hello everyone! I am trying to program my Arty-7 A35T FPGA using OLIMEX-ARM-USB-TINY-H, can I do this or not? If yes then How?
  19. Hi, I am planning to load a RISC-V Rocket SoC into a Genesys2 Kintex-7 FPGA, the RISC-V Rocket SoC has a JTAG interface which allows the "outside world" to access logic in the SoC, such as reading some internal registers. I am thinking I'll route the RISC-V JTAG interface to the JTAG port of Kintex-7, which is then connected to J17 USB of the Genesys2 board, On the other hand, I want to run chipscope to view internal signals of the RISC-V SoC for debugging purposes. This would require connection between host computer and the FPGA, the connection used is typically through the JTAG port. My question is do you think I can use Kintex-7 JTAG port for both functions mentioned above? Thanks, Edwin
  20. Hi All, We are using Zynq UltraScale+ RFSoC FPGiA.(FPGA Part :-- XCZU21DR-1FFVD1156) Please suggest a JTAG programmer which supports flashing of XCZU21DR-1FFVD1156!. Also if please let us know if there is production programming support also!
  21. Hello I tried HelloWorld example in Vitis and Vivado 2019.2 and this worked well until programming FPGA. Because I have only one USB cable to connect into zedboard PROG port or UART port, I ran a HelloWorld program with "RunAs -> Launch on Hardware(System Project Debug)" with connecting cable to PROG port and reconnected to UART port to receive outputs from zedboard. However, I got weird results(e.g. there is no outputs or there is outputs but garbled). After that, I borrowed a cable from my friend and also connected it to zedboard, and I rerun program and got appropriate outputs. My question is whether I must have two cables to connect two ports when programming FPGA and run program by jtag. If not, please tell me how to do that.
  22. Hello, I have a Zybo Z7-10 board, where the USB port does not seem to work at all anymore. Af far as I can remember I used it 2 Years ago and back then I could at least connect via JTAG to the Vivado HW Manager. But right now UART and JTAG do not work. I also tried the provided binary from this thread (https://forum.digilentinc.com/topic/20132-zybo-z7-usb-uart-no-longer-recognized-by-pc/). And even the "DONE" LED does not turn on. When I boot from QSPI and start the pre programmed demo, the board lights up and all the LEDs are flashing. So the board seems to work in general. But als during the QSPI demo there is no serial connection. On my host PC I don't see any message in dmesg as well. Is there anything that I could try to make it work or debug the issue further? Regards, Erik
  23. Dear friends, We have intended to use the JTAG-SMT3-NC module for both FPGA and ARM MCU programming. Our planned configuration is channel A for FPGA programming and channel B for ARM MCU programming. Do you please notify us if we are capable to perform the above work or not? Also, can we configure as JTAG the both channels (A and B)of the JTAG-SMT3-NC module with FT_PROG software. If not, please advise the solution. Also you can submit your tender to eliminate this difficulty. Attached please find the our working configuration. Wait for your response. Sincerely yours,
  24. Hi, I'm using JTAG-SMT3-NC for JTAG and UART on a custom board. One of the boards has a very strange behavior when sending UART serial to the board. The character 'U' doesn't work, but all other keys work fine. Digging into it a bit further, I can see with a scope that the UART signal is incorrect for the letter 'U'. Please see attached scope plot. The upper (white) trace is when the 'U' key is pressed. Please compare this to the lower (yellow) is the 'A' key. Manually decoding, the 'A' waveform is correct (0x41), but the 'U' is incorrect (0xd5 instead of 0x55). A few other notes: Same behavior on two totally separate laptops (windows10) Same behavior at different baud rates. 115200 baud, 1N8 normally used. The 'U' key works as expected on ~10 other boards we used. Seems like something "happened" with this one. All other letters appear correct, and have their MSB cleared. Could anyone think what might cause this behavior? UART trace U vs A.bmp
  25. greg751

    CMOD S6 JTAG

    HI everybody, Did anybody suceed to program CMOD S6 thanks to the JTAG header ? I'm trying desperatly to initiate the JTAG chain without any success ! With I used the USB connexion, it works perfectly. I wanted to try the platform cable USB from Xilinx to configure the FPGA like shown on the following picture : I got the following error : There is something that "puzzles" me in the CMOD S6's schematic... I put the parts of the schematic concerned by my interrogations in the attached file (PDF). I noticed that there are physical links between J4 header, IC3A (Atmel) and IC5A (FPGA) for the following signals : TDI-FPGA TDO-FPGA TCK BUT regarding the TMS signal, there is a physical connexion only between the IC3A (Atmel) and the IC5A (FPGA). On the J4 header, the signal that should be TMS, is called ISP-Reset. This signal is kept at 3.3V thanks a pull-up resistor and goes into the IC3D. I used an oscilloscope to observe the TMS signal (during the Initalization JTAG chain phase) on IC5A (FPGA) in two different cases : 1°) by using the on board USB => the TMS signal changed 2°) by using the paltform Cable USB 2 => the ISP-reset signal changed BUT the TMS signal did not change... In both the cases TDI-FPGA, TDO-FPGA and TCK changed This could (maybe) explain why it is not possible to configure the FPGA directly by the JTAG header... Does anyone have an explanation about this issue ? Thanks a lot, Kind regards, Greg. cmods6_Partial_Sch.pdf