JColvin

Hi @MicNZh, I have sent you a PM. Thanks, JColvin

Hi @boris_skier, It's unlikely to return since Digilent wasn't the manufacturer of this particular product (it was NKCelectronics), but it appears their website is no longer readily available. I will mention that there is interest in creating such a product, though to be honest for one-off projects it would probably be more effective for users to create own shield in exactly the way they desire based off of the dimensions taken from the 3D model of the Arty A7, https://digilent.com/reference/programmable-logic/arty-a7/start#additional_resources. Thanks, JColvin

Hi @Airmanblu, I don't have a Pmod CLS with me at my home office to test this, but you are correct that MO0 should be the only jumper that needs to be loaded with regards to JP2. You'll also need to set JP1 to the SS side so that any Chip Select signaling gets routed to the correct pin on the embedded microcontroller. The supplied 3.3 V from the myRIO should be fine. Thanks, JColvin

Hi @BigBob, I moved your thread to where the WaveForms developer will be able to more easily see your suggestions and feedback. I'm not the developer, but do have a couple of clarification questions. Could you explain a bit more of what you mean by "Live-Data"? Are you referring to effectively watching a .csv file being created "live", or something else? And I guess more relevantly, what feature are you imaging this other software receiving the analog/digital data doing that WaveForms does not currently support? The software-trigger I am imagining to be somewhat controversial as it is inherently slower than the trigger bus that is implemented in hardware, so by the time a Math trigger is detected, the hardware condition you want to catch could have already passed. What sort of timing resolution would you be envisioning with this? Thanks, JColvin

Welcome to the Forum!

Hi @RakeenJ, I apologize for the delay. I was out of office all last week. It appears you have overwritten the EEPROM like many other users: I have sent you a PM with some instructions. Thanks, JColvin

Hi @jowell88, I apologize for the delay regarding on questions 2 and 3; this is the clarification that I have received. C177 and C178 are both present because VrefCA and VrefDQ as per the Micron datasheet (https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_1_35v_ddr3l.pdf) on Table 22 expect to have voltages of Vdd/2. DDR3_Vref sources this from a voltage divider (middle of page 10 of the Zybo Z7 schematic), and then the combination of C177 & C179 and C178 and C180 provide further stabilization of this voltage as required by Table 21 and Table 22 of the Micron datasheet. Addtionally, VrefCA and VrefDQ should track any variations on Vcc1V35. So the two equal-value capacitor pairs will represent relatively small impedances for short-term variations from Vcc1V35, effectively forming voltage dividers that cause short-term variations on Vcc1V35 to be tracked by both Vref inputs. You are correct that the EXTEST operation will not work on the Zybo Z7 as per the note Table 5-3 in UG933 and the corresponding answer record (https://support.xilinx.com/s/article/57930?language=en_US). There is no way to temporarily change the bank voltage on MIO1/Bank 501 from 1.8 V to any other value on the Zybo Z7. Let me know if you have any questions. Thanks, JColvin

Hi @jcbdev, I have sent you a PM. Thanks, JColvin

Hi @YongBin, Digilent doesn't have anything designed for the ZC706 from Xilinx, but there are a couple of example projects for the FMC Pcam Adapter, https://digilent.com/reference/add-ons/fmc-pcam-adapter/start#example_projects, that use the Zedboard (a Zynq 7020 based board) that might be feasible to port to the ZC706, though I haven't looked into how different the ZC706 is. Each page for the example projects has a link to their respective GitHub repositories with the source code. Thanks, JColvin

Hi @ctkilian, The module not drawing any current (I'm not sure how you are measuring this) is not necessarily a red flag since as per the datasheet of the onboard IC, https://www.renesas.com/eu/en/document/dst/isl29501-datasheet, it is only drawing at most 2.5 uA during sleep mode which the module is put into after a STOP condition after a Read command or after a write command has completed (page 13). By default, the module is primed to be going in free running mode (register 0x13 bit zero) but it requires a trigger (pulling the sample start, pin 2, from high to low) before this occurs (page 16). As for addressing the module, sending 0xAE is correct if you want to do a write command (since write would put that last bit low); the module should respond with an ACK after receiving the chip address, though if you send a Stop condition from the host prior the completion of the data byte and the corresponding ACK from the Pmod, the Pmod ToF (or more specifically, the ISL29501) will reset itself back to sleep/standby mode. Let me know if you have any questions. Thanks, JColvin

Hi @yunzhenghan, I haven't used Petalinux, but it should already be pulled in for you when you import the .xsa file from Vivado. The basic flow for the OLED driver is mentioned in this thread here: Let me know if you have any questions. Thanks, JColvin

Hi @RyanW, My understanding is that the firmware on the Platform MCU which controls the state of VADJ will by default/on power up will have the VADJ rail disabled until it parses the EEPROM memories of the attached device to determine the correct VADJ to use. An LED fault indicator will be shown and the VADJ rails will remain disabled if no compatible VADJ voltage is found (such as if an FMC mezzanine module and SYZYGY pod have mismatched values, or request a VADJ that the Genesys ZU is not able to supply). I have asked another engineer more familiar with the Genesys ZU what additional actions you can take to help ensure the correct voltage upon power up. Thanks, JColvin

Hi @Zhang416, Thank you for the information. From my understanding, even if you were on the high gain setting for the Zmod Scope (+/-1 V input range) when applying the 2 V square wave (presuming the Eclypse Z7 & Zmod were sharing a common ground with whatever device was generating the 2 V signal), the Eclypse Z7 should not be damaged by this, or at least not the 1.8 V rail. If you purchased the board directly from Digilent and wish to exchange it, please send me a private message with the following information: - Order Number - Purchase date - Board Serial number (barcode sticker on the underside of the board starting with "D") - preferred email contact so I can get the information to our Sales team who will then follow up with you to confirm any additional information from you, such as shipping address, that I don't have access to. If you instead purchased the board from a distributor (Farnell, Amazon, etc) you will need to contact that distributor directly for their own RMA process. The distributor will then contact Digilent directly as needed. Feel free to reference this thread as having done troubleshooting with a Digilent engineer. Thanks, JColvin

Hi @Zhang416, In the interest of avoiding confusion or presuming inaccurate information, I'm still going to ask for a more specific set of voltages; a more contained list of the voltages as well as a reference image for their location is in this post: Could you also let me know a bit more what you were doing with the Pmod port? Just using it with some module, using it plus a Zmod, something else? Thanks, JColvin

Hi @aceblen, I'm not certain which version of Vivado you have or which Pmod tutorial you might be using (I'm presuming this one that was made for pre-Vitis era, https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start). I don't know what you mean by opening up an IP core in Vitis, but in terms of getting most Pmod modules working in newer versions of Vivado (I haven't tested any Pmods with 2023.2 with its new underlying IDE), but in general the approach in Vitis is largely the same as SDK. The only major difference is that when adding in the IP core to the Block Diagram in Vivado you'll need to right click on the output of the Pmod IP and choose to make the output external. You'll then create a .xdc file that matches the pin names of those external pins (names of which can be found in the wrapper after you have Vivado validate the Block Design and create the wrapper for it). There is some more detail about this process in this thread: Let me know if you have any questions. Thanks, JColvin

Hi @jowell88, 1. Digilent has made the choice not to provide the details about the implementation of this in our boards. You can read more about it some other threads such as these two: https://forum.digilent.com/topic/20362-usb-proguart-schematic-request/, https://forum.digilent.com/topic/27253-schematic-for-original-arty-missing-usb-connector-and-ftdi-chip/. I will get clarification on questions 2 and 3 to make sure I'm not providing misinformation. Thanks, JColvin

Hi @AWann, D10 is the correct pin for sending serial data out of the Arty A7 board; though the naming convention (perspective of host computer as the DTE) isn't always ideal. The direction of the pins should be clarified in Figure 8.1 of the Reference Manual though: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#usb-uart_bridge_serial_port. Like zygot mentioned, I'd also be double checking the baud rate for your Microblaze setup to make sure it matches what was configured in the block design (9600 baud by default when using the Digilent board files and general design flow outlined here: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi). There is also an HDL GPIO demo for the Arty A7 that sends serial data to the host computer available here: https://digilent.com/reference/programmable-logic/arty-a7/demos/gpio, that you can compare to as well aside from the material that zygot referenced in the other thread. Let me know if you have any questions. Thanks, JColvin

Hi @sadrannan, Does the Zybo Z7's red power LED turn on after you connect the microUSB cable and flip the power switch (presuming you have the jumper set to USB power instead of wall power)? I am presuming that by device manager you are referring to Windows Device Manager. If you are not seeing any change in the Windows Device Manager, this implies to me that there is no data being transferred over the USB cable and would recommend trying a different USB cable. There is some additional information on what you should expect to see in the Windows Device Manager in this thread here: Let me know if you have any questions. Thanks, JColvin

Hi @Nick Conklin, The datasheet for the embedded ADC081S021, specifically section 8 and Figure 2 in section 7.6 https://www.ti.com/lit/ds/symlink/adc081s021.pdf, will be of the most help for figuring out how the TI ADC organizes it's data. Many years ago (clarifying this detail since this document isn't linked on the resource center nor been looked at for accuracy), I wrote a bit of extra information on how the 8-bits of usable data are organized in the 15 bits of data from the ADC here: https://digilent.com/reference/pmod/pmodals/user-guide#communication_protocol, though I think I replicated this information in the Interfacing with the Pmod section of the Reference Manual, https://digilent.com/reference/pmod/pmodals/reference-manual. Regardless, I do not disagree that the information is hard to parse. I will see about getting some sort of timing diagram into the reference manual if I get the opportunity. Thanks, JColvin

Hi @Simon Koops, Unfortunately, there really isn't one outside of getting the XUP USB JTAG programming to work on newer Windows. There are a number threads discussing this: https://forum.digilent.com/topic/26104-programming-xilinx-cpld/ https://forum.digilent.com/topic/158-programming-cplds-with-hs1-or-hs2/ https://forum.digilent.com/topic/23686-program-cpld-with-xup-usb-jtag/ https://forum.digilent.com/topic/350-jtag-usb-versus-jtag-hs2/ However, the XUP USB JTAG does work on Windows 10, though it's been a few years since I've specifically tested this out. Let me know if you have any questions. Thanks, JColvin

I have sent some PMs. Thanks, JColvin

Hello, Yes the Vivado Hardware Manager will automatically claim JTAG access over Adept to the JTAG HS3 (and other Digilent JTAG programmers). You would have to the Vivado hwserver.exe closed in order for the JTAG HS3 to remain connected to Adept or a non-Vivado solution. As for the serial terminal portion, the JTAG HS3 does not support a serial terminal connection where you can have UART data be sent over the module, https://digilent.com/reference/programmers/jtag-hs3/reference-manual. You would need a different module that supports such connections, such as the JTAG SMT3, https://digilent.com/reference/programmers/jtag-smt3/reference-manual. There is a way to use BSCAN primitives to get serial data over JTAG lines within Xilinx SDK/Vitis, but Digilent does not have any support for getting this working within the Xilinx software suite. Let me know if you have any questions. Thanks, JColvin

I have sent you a PM.

It looks like Petalinux wasn't able to access a number of different repositories, which can happen for a variety of reasons. I'm not certain what issue might be in your situation specifically, but here are a number of other threads that might help you find the source of this: thread1, thread2, thread3. Thanks, JColvin

Hi @Tparng, I apologize for the long delay. I'm not certain why djtgcfg is not successfully configuring the Zedboard. It's not particularly helpful to you, but I am able to successfully configure the Zybo Z7-20 I have on my desk with the Adept GUI (which I was told by the developer uses the same underlying API calls that djtgcfg uses). Is there a particular reason that you want to use dtjgcfg when Vivado is already working to configure the board? Thanks, JColvin