JColvin

Hi @harshana, This is very strange that the Power Good LED (LD13) is not glowing, but the board is still able to be detected and that the Ethernet LEDs are lit up. Are the user LEDs (LD0 through LD7) flashing in a pattern you configured or does it appear to be sporadic? More strangely, the picture of the Zedboard that you sent me has the 5 MIO jumpers all set to ground, so the board should only be configurable through JTAG. What is confusing to me is that as per page 15 and 16 of the Zedboard schematic, https://digilent.com/reference/_media/reference/programmable-logic/zedboard/zed_sch_rev_f1-public.pdf, the power good LED will only turn on if PG-ALL is enabled. But this pin only becomes enabled if all of the other voltage rails (which ultimately are only enabled if the 12 V supply is accurate) are correctly powered on. Additionally, the Ethernet LEDs should not be on when there is no cable plugged in as one only lights up when there is an Ethernet connection, and the other indicates activity. Neither of these conditions are true and both are internally controlled by the Ethernet controller chip (as opposed to the Zynq). By and large, the Zynq also operates at 3.3 V (which is what the Power Good LED uses), so the fact that the Zedboard shows up in the Vivado Hardware Manger is also unexpected. Unless there are additional details that I am missing, I can really only recommend the following: - Ensure you are using a 12 V power supply of sufficient wattage (I'm using a 12 V, 3 A supply) and that the supply is outputting the correct voltage - Check that there isn't any weird debris on the board - Put the Out of Box demo, available here: https://digilent.com/reference/programmable-logic/zedboard/start#additional_resources, onto the SD card - Set jumpers MIO 5 and MIO 4 to the 3.3 V settings so that the Zedboard will boot from the SD card - Set your VADJ jumper to either the 1.8 V or 2.5 V setting (to be clear, I strongly doubt this will do anything, but it won't hurt) - Turn the Zedboard back on and see if the Power and Done LED turn on and that you get activity through the UART port on J14 at 115200 baud If this does not change the behavior, then I do not know what is happening with the board and would recommend that you pursue at return (presuming the warranty is in place). Thanks, JColvin

Hi @erick.chang, I will ask the engineer most experienced with Adept for their insight into this question when I get the chance (they are out of office until October). My guess off-hand is that one of the enumeration calls are done in the background to populate the dropdown list in the top right, which then acts as the string/correct identifier for an DmgrOpen command of some kind when the Initialize Chain button is pressed, but I don't have any insight that I can claim as fact as to what the application actually does. Thanks, JColvin

Hi @SCguy, Unfortunately, Digilent has made the decision not to share this detail of our products. You can read more about it in this longer thread here: Thanks, JColvin

Hi @Batgerel, My understanding as a non-Xilinx employee is that the Xilinx toolchain is subject to the US Export Compliance: https://support.xilinx.com/s/article/44043?language=en_US. If you are not able to appeal with Xilinx in order to be able to download and install the Xilinx toolchain, I strongly recommend that you return and get a refund for the Nexys A7 board as it will not be usable without access to the Xilinx software suite. If you purchased the Nexys A7 through a distributor (such as Avnet), you will need to contact them to determine their RMA process. If you purchased the board directly from Digilent, please send me a private message with the Order Number, Serial number of the board (located on the barcode sticker on the underside of the board that starts with the letters "DA"), Purchase date, and preferred email address contact so I can get the information to our sales team to start the return process. Let me know if you have any questions. Thanks, JColvin

Hi @ekallal, I'm not familiar with this install_digilent.exe that is apparently with the Lab Edition, so I don't know what it does (as far as I am aware, Digilent did not make this executable), but I'm presuming it operates as the same as installing the Digilent Cable drivers: https://support.xilinx.com/s/article/59128?language=en_US. Otherwise, I would recommend installing Adept, https://digilent.com/reference/software/adept/start, as that is where Xilinx gets the cable drivers from, so it would be akin to installing from source. The download for Adept will take you to a MyProducts page and ask you to log into the Digilent Cloud; if you have a login for the Digilent store, this will be the exact same login for the cloud. Let me know how it goes. Thanks, JColvin P.S. I figure you know this, but just to clarify that Vivado will not be able to target the JTAG HS3 on its own as there is no FPGA on it; I believe it will show up in the Hardware Manager as something to connect to though.

Hi @Ansh Waikar, Personally, I probably would have used the 2022.1 release if you have the 2022.2 version of the Xilinx toolchain since it's going to be easier to debug while upgrading rather than debug if forced to downgrade, but I digress. What you are describing sounds like the Xilinx linker script import bug; normally Digilent has a dedicated dropdown section on this included in our guides, but it is apparently missing from this Zedboard demo. I've added the relevant section into the guide you linked; it's expansion box called "Apply Fix for Linker Script Import Bug". Hopefully this isn't the case for you, but then I had to fight with Vitis further since it said it couldn't find a .h file that was in the same directory as a different header file. I ended up resolving this by right clicking on the imported FMC_Pcam_Adapter_demo, selecting Properties, going to Paths and Symbols in the C/C++ General dropdown, and editing the offending non-existent directory to the correct file system folder. In my case, I had to change the C:/Temp/whatever_it_was to D:\VivadoPrj\Zedboard-Projects\FMC-Pcam-Demo-23.1-R\Vitis\FMC_Pcam_Adapter_demo\src (the beginning of the path should be changed to whatever is accurate for your computer, of course) where the the first portion up until FMC_Pcam_Adapter_demo\src is where I had set up my Vitis workspace. Let me know how it goes for you. Thanks, JColvin

Hi @Niranjana, This message appears when the FPGA / SoC has not been configured with a bitstream. More recent versions of the Xilinx software have made it so that when you choose to launch an application it will automatically load the bitstream for you prior to launching (used to be that you had to manually configure the device with the bitstream). I don't know which version of the Xilinx / AMD toolchain you are using, but you can still manually configure the device with a bitstream by clicking Xilinx / Vitis dropdown at the top (next to File, Edit, etc) and choose the Program Device option. Presuming you first created a hardware specification (block design) in Vivado and imported it into Vitis, my guess as to why Vitis is not automatically finding the bitstream is because after exporting the hardware platform, the include bitstream option was not checked. Let me know what you learn. Thanks, JColvin

Hi @Ni-cool, You are correct that the mechanical drawings of the Analog Discovery 3 do not include any details on the internal dimensions nor is there a 3D model available. I will ask again to see if such material can be made available, but I wouldn't recommend holding your breath over it. Thanks, JColvin

Hi @John Michel, If you want to view the sniff some external I2C bus data flowing through a larger external daisy chain, I would use the Logic Analyzer to add (via the green plus button underneath the "Single"/"Run" buttons to add a pair of pins for the SCL and SDA lines, which you would then connect to the existing daisy chain. You can then just have the device run to capture data, or if you want to capture specific material you can set up a Protocol trigger to look for a particular address and data byte combination. If you need to adjust any of the pins to have pull-up resistors, you can do that for each individual pin within the Supplies tool, or through the Device Options which is accessible either via the 100 MHz dropdown at the bottom of the screen or within the DIOs tab in the Settings -> Options at the top of WaveForms. The challenge with using the Logic Analyzer for I2C is that I2C devices tend to a have a relatively large amount of downtime between transactions, so you'll end up using a comparatively large timebase to capture the entire sequence and then be using the arrow buttons on the plot to have the screen scroll for you between events. Within the Protocol Analyzer instrument, you also use the I2C option to sniff all I2C traffic or choose to only receive data sent to a particular address (via the filter checkbox), as well as having the option to have the Digital Discovery as a controller to send your own traffic. The catch then becomes that you are more limited in your trigger options as well as being limited to only working with a single protocol at a time, whereas using the Logic Analyzer directly, you can add any number of different protocols (until you run out of pins on the Digital Discovery anyways). As always, additional information about the various settings is available in-app within the Help tab. Let me know if you have any questions. Thanks, JColvin

Hi @otherguy, I can't speak towards Attila's physical circuit setup outside of him having used the Impedance Adapter (https://digilent.com/reference/add-ons/impedance-analyzer/start, which uses 0.1% reference resistors) that was plugged into an Analog Discovery 2, but the dotted vs solid lines are there to differentiate which type of calculated measurement is being represented over the range of frequencies, with the different line patterns being shown underneath each toggle-able measurement type: In terms of the software side setup, it's simply a matter of selecting the "Impedance" tool from the Welcome tab and then clicking on the various plots you want to see and adjusting the various values in the visible dropdowns. Additional explanations of each of the settings are available within the Help tab in the Impedance section. If you wanted to try it out, the latest beta is freely available for download and has a demo modes for the different hardware options here: Let me know if you have any questions. Thanks, JColvin

Hi @GregoR, Attila is the expert on these devices, but I wanted to reiterate that we got confirmation from the manufacturing side that these are indeed just jumpers that are normally removed after the initial programming and that you can remove the rubber feet to get access to the screws on the housing without voiding warranty. Digilent will make sure that these jumper blocks are removed in the future. Thanks, JColvin

Hi @Michael Gordon, I'm guessing you already installed the cable drivers on your system (https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_cable_drivers_linux_only) and your output is accurate, so I'm not certain what why Vivado would not be seeing the Basys 3 in Ubuntu 22.04 at the moment. I'll keep doing some research to see if I can come up with something. Thanks, JColvin

Hi @Wiliam, I have sent you a PM. Thanks, JColvin

Ah, I think you would have needed to choose the "Check for beta" option within the Help menu, since 3.20.1 is technically the latest release, but with lots of people using the software, more fixes, changes, and additional features keep getting added.

Hi @Dmitry, Are you able to download and install the Adept System, https://digilent.com/reference/software/adept/start? Xilinx gets the Digilent cable drivers from Adept, so this would be akin to installing from source. With regards to downloading Adept, if you have an existing Digilent store account, the login for the Digilent Cloud (which is where the Download now button will take you to) will be the exact same as the existing store login. Let me know if that doesn't get the drivers working so we can debug further. Thanks, JColvin

Hi @nvdatx1, Digilent doesn't share the bom file for our boards, but the connector you are looking for is a USBC-FC05RB2N4, which I believe comes from LianShuoElect (or that's the manufacturer source that I see listed). There are some mechanical details for it in this post here: Let me know if you have any questions. Thanks, JColvin

I think I found the problem and solution, but I'll walk through what I did. BLUF, you'll probably need to add the following line to your .xdc: I also added the following two lines, but I don't believe these are strictly necessary: Vivado added these three lines for me by opening up the Implemented Design, then going to Project Manager Settings -> Bitstream -> Additional Bitstream configurations, making the changes in the various tabs, then saving the Implemented Design to update the .xdc, but I plan on simply typing them into the .xdc in the future. Long version of how I got there is: I set up 4 different boards to test out with various Vivado installs: Basys 3 - Spansion flash, HDL, no UART (I'm treating this one as a pseudo-control variable) Cmod A7 15 - Micron flash, processor, UART Cmod S7 25 - Macronix flash, HDL, UART Arty A7 100 - Spansion, HDL, UART After I confirmed that their flash projects worked as is (i.e. operated as expected after disconnecting and then reconnecting power with no instance of Vivado or Adept or hwserver.exe opened), I opened up different instances of Vivado one at a time and individually tested to see if each board would start their flash program either with or without the Hardware Manager having specifically selected that board as a target. My table of results that I got off of my machine (Windows 10, fwiw) is below: Clearly, with the designs in their current state, the Cmod A7 and Arty A7 needed to be reset before they started working, but that evidently doesn't apply to the Basys 3 or the Cmod S7. The Basys 3, Cmod A7, and Cmod S7 were all running their original out-of-box designs and the Arty A7 was running a rebuilt version of its out-of-box demo. Since the Cmod S7 and and Cmod A7 are very similar I decided I'd port the existing Cmod S7 out of box demo (https://digilent.com/reference/programmable-logic/cmod-s7/demos/oob) to the Cmod A7, upgrading the design to 2023.1 in the process. As a sanity check before porting, I had Vivado upgrade the project to the newer version of the tools (Vivado had to do some directory restructure), ticked the box for a .bin to be created, added the Macronix memory configuration part to the listed Spartan 7 in the Hardware Manager, and suddenly found that the configuration stored in flash did not load unless it was not being targeted by Vivado. That was enough for me to remember the additional bitstream flash settings I mentioned at the beginning of this post, so I regenerated the bitstream with these new settings which did have the part successfully load. (Or I guess, to be clear, when I initially programmed the memory configuration device, it did not boot from it that very first time. I had to select boot from memory configuration device, or disconnect the device entirely from power first before it then started to consistently boot from memory on POR) With that success, I ported the design to the Cmod A7 15T (attached), made sure that the various bitstream / property settings were in place, and found that now the Cmod A7 also booted successfully, even when it was being targeted by the Vivado Hardware Manger. So, basically any version of Vivado where the Xilinx Hardware Manager now automatically reconnects to the device (first occurring sometime in the 2016.X era), you'll need that extra CONFIG_MODE property set for the device to have SPI flash always be a configuration mode option. As for why auto-reconnecting to the device prevents booting up from flash when it can successfully boot in all other scenarios, I have no idea. Thanks, JColvin CmodA715-S7-OOB-Port-23.1.xpr.zip

Hi @Leon18, The AMS header / XADC header on J2 is accurate; there is an existing silkscreen printing indicating the corner location of pin 1 (also indicated by the square pin on the underside of the board) that corresponds to Vn as per Table 17 of Avnet's Hardware User Guide as well as the schematic of the Zedboard (lower left corner on page 2): https://digilent.com/reference/programmable-logic/zedboard/start#documentation. I do not know why the diagram presented in Avnet's documentation is rotated 180 degrees from how the hardware has existed since it first launched in 2013. Thanks, JColvin

Hi @reddish, I don't have any immediate ideas as to what might be the situation. I've posted on a number of different threads over the years about how I've fought with Vivado / Vitis to get an SDK / processor based project to run off of flash (Kvass linked to some of tje,), but when I plugged in my two Cmod A7's into my host computer this morning (no instance of Vivado open), Tera Term is happily reporting that the SDK flash programs are being loaded. Regrettably, I didn't have the foresight at the time to have the name of the Vitis project be printed out over terminal, so I don't know off-hand what project I used, though it looks like both the -35T and the -15T boards I have both have Micron memory rather than Macronix (-35T has some custom flash project, -15T is running the out of box project). I think one of the Cmod S7's I have might have the Macronix memory (and I think @artvvb got a Cmod A7 with a Macronix memory somewhat recently, though he is out of the office today), so I will do some testing to see what I can come up with with regards to straight HDL flash projects. Though fair warning in advance that if this appears to be some sort of change due to in various Vivado versions, I'm going to be rapidly out of ideas as to what the resolution will be (aside from not having the device be snagged by the Vivado Hardware Manager) as Digilent (or at least certainly not me) does not have any special access Xilinx representatives. Thanks, JColvin

Hi @Prakash, I don't know what your intended application is with Arty Z7 board or your level of experience in this field, but I would recommend taking a look at the Arty Z7 Resource Center, https://digilent.com/reference/programmable-logic/arty-z7/start, where Digilent has curated a number of resources for this board including some tutorials and example projects. Since you mentioned that you are using a different FPGA (an Artix 75T), using a Zynq SoC device will be similar with regards to using the Vivado and Vitis UI, but unlike an FPGA, interfacing with different features on the board (such as UART for a serial terminal or DDR memory) are abstracted away and tied to the ARM core processor that is present on the Zynq device, giving you some premade convenience at the more limited low level configurability. Let me know if you have any questions. Thanks, JColvin

Hi @B Algera, I have sent you a PM. Thanks, JColvin

Hi @tBarber, I have sent you a PM. Thanks JColvin

Hi @Michael Gordon, I'm not a Linux expert, but this looks very similar to the upstream Linux bug that got reported here: Let me know if this is not the case for you so we can debug further. Thanks, JColvin

Hi @Eleni, I would use the Record to File option in the Scope instrument (the "Rec." button underneath File/Control/View, next to "Export") for long recordings. I'm not certain what you are wanting with the " is there a way to record at 1kHz but save only the average over 100 samples in a csv file?". Are you wanting to record at some rate and then, for the lack of a better word, compress all of the data into 100 different samples? Or record at a rate, but only pick 100 different samples? Or is this more along the lines of the device operates at some sample rate over 100x of my recording rate, can I get an average of 100 different samples per time slot? The ADC used in Digilent devices operates at a fixed frequency (the system clock frequency, 100 MHz by default), so if you set the sample rate to a lower value, the device will average acquired data for a particular timeslot based on the time base and the buffer size. Alternatively you can choose to decimate where you only capture every Nth sample. I'm not certain off hand how the Record to File option determines the timebase and number of samples; the creator of the WaveForms software (Attila) should hopefully be able to give a bit more insight into that. Thanks, JColvin

Hi @DBanks60, I don't have a Design Edition installed, but my understanding is that as long as the Design Edition allows bitstream generation for the correct Xilinx chip (I haven't checked, but I don't think vouchers for Design Editions differentiate between speed grades or something like that), then it should work. There should not be any additional, paid IP that is required to run the HDMI demo, https://digilent.com/reference/programmable-logic/genesys-2/demos/hdmi. Let me know if you have any questions. Thanks, JColvin