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Found 17 results

  1. Hi, I just got nexys video and was going down the list of out-of-box demo at the bottom of its reference manual : https://reference.digilentinc.com/reference/programmable-logic/nexys-video/reference-manual When I connect the ethernet cable, ACT/LINK/USER LEDs blink for a bit, then LINK/USER blink in sync indefinitely, but there's no IP address displayed on OLED screen, just shows 0.0.0.0 I tried checking things on my router side (Netgear), but there is no indication of the device in its logs. Are there any way to confirm that the ethernet is working properly?
  2. Hi there, I am quite new to FPGA and would like first to apologize if my question is *stupid* :-) I have read already quite a lot and I am kind of stuck. Any help appreciated ? Hardware Card: Nexys Video Vivado 2016.4 What I would like to do I have an external TTL signal (3.3 V, 1 kHz) connected to the Pmod A, ja[0] pin (and the ground to GNB) . As a test, I would like to read this signal, fill a FIFO and then read the FIFO buffer when the buffer is full. I do not mind to lose data; I just want to see (on the computer) some raw data once in a while. ISSUES From the SDK terminal, I receive weird data like "²’ÒŠRj$ª²šÒŠRj$ª²¢". My top module `timescale 1ns / 1ps module oscillo(clk, uart_rx_out, TTL_in,sw); input clk; input sw; input [0:0] TTL_in; // These are input data output uart_rx_out; reg [0:0] TTL_in_reg; always @(posedge clk) TTL_in_reg <= TTL_in; wire [0:0] q_fifo; // These are output data fifo_generator_0 myFifo ( .clk(clk), // input wire clk .din(TTL_in_reg), // input wire [0 : 0] din .wr_en(wrreq), // input wire wr_en .rd_en(rdempty), // input wire rd_en .dout(q_fifo), // output wire [0 : 0] dout .full(wrfull), // output wire full .empty(wrempty) // output wire empty ); // The flash ADC side starts filling the fifo only when it is completely empty, // and stops when it is full, and then waits until it is completely empty again reg fillfifo; always @(posedge clk) if(~fillfifo) fillfifo <= wrempty; // start when empty else fillfifo <= ~wrfull; // stop when full assign wrreq = fillfifo; assign rdempty = ~ fillfifo; microblaze_mcs_0 myMCS ( .Clk(clk), // input wire Clk .Reset(sw), // input wire Reset .GPI1_Interrupt(GPI1_Interrupt), // output wire GPI1_Interrupt .INTC_IRQ(INTC_IRQ), // output wire INTC_IRQ .UART_txd(uart_rx_out), // output wire UART_txd .GPIO1_tri_i(fillfifo), // input wire [0 : 0] GPIO1_tri_i .GPIO2_tri_i(q_fifo) // input wire [0 : 0] GPIO2_tri_i ); endmodule My xdc file ## FPGA Configuration I/O Options set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { TTL_in }] ## Board Clock: 100 MHz set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; create_clock -add -name clk_100m -period 10.00 [get_ports clk] ## Reset Switch set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw}]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }] My helloword.c for the sdk #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xparameters.h" // add #include "xiomodule.h" // add volatile char int_flag = 0; // millisecond counter variable //function which is called by the GPI interrupt when one of its bits goes hi void MyInterruptFlagSet( void* ref) { int_flag = 1; // when it receives interrupt, set c } int main() { init_platform(); u32 data; u16 my_secs = 0; XIOModule gpi; //print("Setting up GPI\n\r"); data = XIOModule_Initialize(&gpi, XPAR_IOMODULE_0_DEVICE_ID); data = XIOModule_Start(&gpi); //setting up interrupt handlers and enables them microblaze_register_handler(XIOModule_DeviceInterruptHandler, XPAR_IOMODULE_0_DEVICE_ID); // register the interrupt handler // Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. XIOModule_Connect(&gpi, XIN_IOMODULE_GPI_1_INTERRUPT_INTR, MyInterruptFlagSet, NULL); // register timerTick() as our interrupt handler XIOModule_Enable(&gpi, XIN_IOMODULE_GPI_1_INTERRUPT_INTR); // enable the interrupt microblaze_enable_interrupts(); // enable global interrupts while (1) { while(int_flag == 0 ) //wait till interrupt flag goes high ; data = XIOModule_DiscreteRead(&gpi, 2); // read counts (channel 2) xil_printf("%d: %d\n\r",my_secs, data); my_secs++; int_flag = 0; //clear flag } cleanup_platform(); return 0; }
  3. Hi. I am planning to include VGA connectivity to Nexys Video project. In that way, I am considering Pmod VGA and, although on web page says "Pmod VGA provides a VGA port to any board with Pmod connectivity ", I have some doubts with that in a context for Nexys Video project. Pmod VGA need two ports near each one, so JC and JB are the only options. The problem with those ports is that each one is labeled for differential pair signals (Nexys Video reference manual) and I think Pmod VGA work only with single ended signals. So my question is, it is posibble to use Pmod VGA with Nexys Video using JC and JB Pmod port? Thanks in advance.
  4. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high throughput and low latency on this board? Is it possible to extend the board with PCIe? To get the full Ethernet capacity, could you please advise if purchasing a TEMAC IP license is advised and at what price? What are the alternative options and industry standards? Many thanks YM
  5. Hello Everyone, We have develop simple imaging system based on Nexys Video development board. We have interfaced Sensor with VGA/QVGA resolution using PMoD ports which provides Monochrome 14-bit data and we are sending this data on Ethernet using UDP packets on PC. We have designed our custom UDP protocol for sending data. Currently we are having Nexys Video board but as per data-sheet this USB port is used for storing programming file. Now we would like start development of similiar imaging system with USB output port. We are new to USB development on FPGA. Can you please share us how to proceed.? How to get started with USB design in Verilog? Is this possible on this board?
  6. Hello, I have a Nexys Video and a Digilent Sevent Segment Display PMOD. I want to drive the Sevent Segment Display using the Nexys Video. The only two matching PMOD headers are JB and JC but they are are marked on the manual (https://reference.digilentinc.com/reference/programmable-logic/nexys-video/reference-manual) as "differential". However, on the Digilent provided XDC constraints file, the pins are individually controllable and marked as LVCMOS33. Can I use those pins as normal single ended PMOD to drive the seven segment display? Thanks!
  7. I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCC Receive the TMDS signals De-serialize them into 10-bit symbols Align the symbols using bitslips Tune the input delays for best reception Convert the TMDS symbols into data values Extract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs) Extract Video Infoframes from the ADP data Extract Audio Samples from the ADP data. Extract Raw Pixels from the VDPs Perform 422 to 444 conversion, if required by video format Perform YCbCr to RGB conversion, if required by video format Convert Studio Level RGB to Full Range RGB, if required by video format Convert Audio smaples to a relative db level Overlay Audio level meters over the video stream Convert the video stream and sync signals back to TMDS symbols Serialize them through a 10:1 serialisers Transmit the TMDS. I think that this is an awesome base for any video experimentation. I've even got to the trouble of making a GitHub repo for it: https://github.com/hamsternz/Artix-7-HDMI-processing Please feel free to fork and extend.
  8. Hi, I followed the instruction in https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start carefully to create the simple echo server with Nexys video board. The vivado version is 16.2. The Ethernet licence is evaluation version. After creating echo server application and run with SDK , it does not run as expected, the output is as follows: -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence link speed: 100 It seems to me the physical interface on the board is not configured right. I tried other lwip application, there is the same problem, so I don't think it is the problem of software or bsp setting. Could you help me ? Thank you very much! Cynthia
  9. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  10. Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also involved setting up a clock backbone route in my constraint file. Instantiation: I've been instantiating my MIG with inputs set to 0 (except clocks) and outputs left open, just trying to get that init_calib_complete signal to go high. clk1 : clk_wiz_0 port map ( -- Clock out ports clk_out1 => clk_ref, -- Status and control signals resetn => reset_n, -- Clock in ports clk_in1 => sys_clk_ibufg); u_mig_7 : mig_7 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => (others => '0'), app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => open, app_rd_data_valid => open, app_rdy => open, app_wdf_rdy => open, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => open, ui_clk_sync_rst => open, -- System Clock Ports sys_clk_i => sys_clk_ibufg, -- Reference Clock Ports clk_ref_i => clk_ref, sys_rst => reset_n ); Constraints: I have one user constraint file bringing in the 100MHz clock from the board as well as buttons, switches, leds, and the audio codec signals for debugging and other functionality. It's attached to this post. MIG setup wizard settings: If anyone has experience with using this MIG or any clocking expertise, please let me know. I've been banging my head against this just hoping for a calibration, and I would really appreciate your help. Thank you!
  11. I am a longtime Actel user in VHDL and want to begin using Xilinx FPGAs. The Nexys Video board looks attractive, but looking at the information on-line I cannot answer some fundamental questions. Does this product include a target specific version of the development environment that allows for design in VHDL? My application needs to use FFTs but I cannot figure out what the utilization per instantiation will be in this device and how much, if any, it will cost for the FFT IP that I can use with this board. Apart from a host computer, what else must I buy to be able to develop VHDL and test VHDL in the Nexys Video? Thank You Gary ggeissinger@digitalglobe.com
  12. Hi, I am playing with the nexys video user demo. I have changed the bitstream to display an overlay (BITC) instead of mouse pointer, and I can bake the bootloader into the bitstream and write it to the flash. I now want to change the microblaze software, which appears to be at flash address 0xa00000. What format image do I write there? Is it the ascii SREC file? James
  13. Is there an example project on how to interface with the SD card slot on the nexys video board? I’m working on a project to decode a .wav file from an sd card to output to the audio codec.
  14. Hi - Looking to use the rgb2dvi_V1_2 module to get video into the FPGA. Vivado is unhappy with TMDS_Encoder.vhd Line 90, as folows: function sum_bits(u : std_logic_vector) return unsigned(3 downto 0) is Generates the following error: ERROR: 'indexed name' is not a type Any ideas on how to fix that? Many thanks, IanM
  15. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  16. I setup my Nexys Video for the first time, and tried to setup an echo server using Vivado/SDK. I followed the following tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start When I go to generate a bitstream, I get the following error: [Common 17-69] Command Failed: This design contains one or more cells for which bitstream generation is not permitted: design_1_i/axi_ethernet_0_U0_mac_U0/tri_mode_ethernet_mac_i/bd_929b_mac_0_tri_mode_ethernet_mac_v9_0_12) If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. The Nexys Video kit did not ship with a special Vivado license, am I required to purchase a license in order to use the Ethernet interface of my board?
  17. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The only downside for Version 1 is that you need a Digilent ATLYS board to serve as the test platform. [Edited] Not 4 hours have passed and I found a silly bug that mis-reported packet size. I've replaced the archive. I also forgot to add the teaser: Wed Oct 17 16:13:03 2018 test_interval_reg = 0x000000000100 >>> Starting test Payload Size = 65536 Total Number of TEST Packets sent = 60000 Total Number of TEST Packets received = 60000 Total Number of TEST Bytes sent = 3932160000 Total Number of TEST Bytes received = 3932160000 Total Number of Errors = 0 Total Number of PHY rxerr Events = 0 Total Duration of the test (in Seconds) = 31.585437952 Percentage Errors = 0.0 TEST packets sent per second = 1899.60956347 Tx Data Rate (Bytes/s) = 124492812.352 Rx Data Rate (Bytes/s) = 124492812.352 ETHERNET_PHY_TESTER_Release_V1A.zip