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Tparng

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  1. @JColvin, If I have Vivado Hardware Manager open and launch djtgcfg, I got the message: ERROR: failed to initialize scan chain With Vivado Hardware Manager closed, it seems that djtgcfg can start programming but failed later and got the following message: Programming device. Do not touch your board. This may take a few minutes... ERROR: failed to program device with file ./build/top.bit Thanks.
  2. I try to use djtgcfg to write bitstream onto Zedboard. djtgcfg started but failed with the following messages: Programming device. Do not touch your board. This may take a few minutes... ERROR: failed to program device with file ./build/top.bit The same bitstream file can be written onto Zedboard and run successfully with Vivado 2022.1 Program Device command. Does djtgcfg work for the fpga device on Zedboard ? BTW, djtgcfg can find my Zedboard as shown below: $ djtgcfg enum Found 1 device(s) Device: Zed Device Transport Type: 00020001 (USB) Product Name: Digilent Zed User Name: Zed Serial Number: XXXXXXXX Thanks, Tparng
  3. @Arthur and Edenwheeler, Thanks for your answers that clarify most of my confusion. One more question: If I created my hardware design from scratch (using IP blocks or rtl modules), exported the hardware, created a new application system and hardware platform in Vitis, and then created my test program starting from the "empty C application" template, do I need to generate a linker script or just use the default one given by Vitis? Thanks, Tparng
  4. The Vitis software platform provides a linker script generator to simplify the task of creating a linker script. When testing the ZedBoard_FMC_Pcam_Adapter_demo app (checked out from https://github.com/Digilent/ZedBoard-SW), if I run the app right after check out form GitHub Repo, it runs successfully. However, after I updated the system_wrapper[Platform] from the new Bitstream produced from the HW project, if I do Generate Linker Script before doing Build Project on the ZedBoard_FMC_Pcam_Adapter_demo app. then the demo app will fail and exit with "terminate called without an active exception" error. If I do not do Generate Linker Script before doing Build Project, then the demo app can run successfully. Does that mean I should not do Generate Linker Script before Build Project or I haven't used the right options/settings for Generate Linker Script command? In general, my question is: Under what situation I will need to generate a linker script for a Vitis Application and under what situation I don't need to ? Thanks, Tparng
  5. @think3, I found the ZedBoard-HW link you provided is valid today and successfully checkout the HW project and build a new Bitstream on Vivado 2022.1. After I updated the system_wrapper[Platform] from the new Bitstream, if I do Generate Linker Script before Build Project on the FMC_Pcam_Adapter_demo app. then the demo app will fail and exit with "terminate called without an active exception" error again. If I do not do Generate Linker Script before Build Project, then the demo app can run successfully. Does that mean I should not do Generate Linker Script before Build Project or I haven't used the right options/settings for Generate Linker Script command? If so, how can I be sure I am building the app with the newly updated hw platform? Thanks, Tparng
  6. @think3, I got 'Not Found' error when I click the ZedBoard-HW link you provided. if I run git submodule update --init on the branch I checked out from https://github.com/Digilent/ZedBoard-HW, nothing happened and I still got the same error messages as above in Vivado. Tparng
  7. @think3, After replacing "avnet.com:zedboard:part0:1.4" with "digilentinc.com:zedboard:part0:1.0" inside project_info.tcl , I got the following error: ERROR: [BD_TCL-109] This script was generated using Vivado <2019.1> and is being run in <2022.1> of Vivado. Please run the script in Vivado <2019.1> then open the design in Vivado <2022.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script. ERROR: [BD 5-229] Please open or create a block design first. ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors. while executing "get_bd_designs" invoked from within "if {[llength $bd_files] == 1} { # Create local source directory for bd if {[file exist "[file rootname $xpr_path].srcs"] == 0} { file mkdir "[file..." (file "/home/tparng/zed-new/ZedBoard-FMC-Pcam-Adapter-Demo/digilent-vivado-scripts/digilent_vivado_checkout.tcl" line 68) Do I need to install a Vivado2019.1 then ? Thanks, Tparng
  8. @think3 and JCovin, Thanks for your help. So far, I can run the FMC Pcam Adapter Demo suceesfully from the system_wrapper[Platform] and elf file pre-built in the Vitis v2022.1 Software Project Repo. However, if I update the system_wrapper[Platform] from a new Bitstream generated from the hw project in archives of FMC-Pcam-Adapter/2022.1-1 zip file, I got the "terminate called without an active exception" again. What could be the cause of this issue? Also, I could not find a checkout.tcl file in the Vivado v2022.1 Hardware Project Repo for checking out the hw project. (I found a digilent_vivado_checkout.tcl in digilent-vivado-scripts folder and tried ways to run it in Vivado tcl console but there were errors and I couldn't create the hw project successfully). I need a way to reproduce the hw Bitstream that can also run the Vitis app successfully. Thanks, Tparng
  9. After more trial and errors, I found that the C++ templates like std::bind and std::make _unique used in main.cc will cause "terminate called without an active exception". Does anyone know what could be the root cause? I am using Vitis IDE 2022.1.
  10. When running FMC Pcam Adapter + 4 pcams Demo with Zedboard, I got got "terminate called without an active exception". This happens when calling AXI_VDMA<ScuGicInterruptController> vdma_a_driver(...) in the following main.cc list. What could be the root cause ? Thanks, Tparng =============================== int main() { //Init CPU, UART, caches etc. init_platform(); #ifdef _DEBUG SET_VERBOSE_FLAG(); #endif VERBOSE("Initializing..."); try {//Constructor of hardware driver classes might throw u8 read_master_select; //Blank VDMA frame buffers memset((u8*)frame_baseaddr, 0x55, (1920*1080*3)*4); VERBOSE("p0"); //Flush D-Cache because this is DMA-accessible memory Xil_DCacheFlushRange(frame_baseaddr, (1920*1080*3)*4); VERBOSE("p1"); ScuGicInterruptController irpt_ctl(IRPT_CTL_DEVID); VERBOSE("p2"); //Construct camera control IPs PS_GPIO<ScuGicInterruptController> gpio_driver(GPIO_DEVID, irpt_ctl, GPIO_IRPT_ID); VERBOSE("p3"); Nop_GPIO nopgpio; PS_IIC<ScuGicInterruptController> iic_driver(CAM_I2C_DEVID, irpt_ctl, CAM_I2C_IRPT_ID, 100000); VERBOSE("p4"); //Dual-channel VDMA for the display and the first camera AXI_VDMA<ScuGicInterruptController> vdma_a_driver(VDMA_A_DEVID, frame_baseaddr, irpt_ctl, VDMA_A_MM2S_IRPT_ID, VDMA_A_S2MM_IRPT_ID); main.cc
  11. Zedboard supports LVDS_25 pins that matches the Meticom MC20901 outputs on the FMC Pcam Adapter. And the demo link shows the Mipi csi2 rx subsystem does work with Zedboard.
  12. As I already purchased FMC Pcam Adapter + 4 Pcam_5C camera modules, to test Xilinx MIPI CSI2 Rx Subsystem IP with them, I better buy another FPGA board "Zedboard", which has a ready-made demo ( https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO)? Thanks.
  13. I am try to test Xilinx MIPI CSI2 Rx Subsystem IP using FMC Pcam Adapter with Genesys2 FPGA board. I have problems with high-speed data and clock signals. While tracing the root cause, I found that the the high speed clock/data MIPI signals on FMC connector LA01_P, LA10_P, LA06_P are connected to Bank 16 of the XC7K325T-2FFG900 (FPGA chip on Genesys2)package pins D26, D29, and B27. Unfortunately, Bank 16 is HR (not HP) bank and does not support internal termination and Genesys2 board does not have external termination resistors on these pins. Without proper termination, FMC Pcam Adapter + Pcams won't work reliable on Ge
  14. By editing my license list in the Xilinx License portal, I finally got the list clean up as below and I can still use Vivado ML Enterprise Edition with Genesys2 board. Thanks a lot for your help.
  15. I do have a permanent OEM _7K325T_DesignEd license (see the black high-lighted row below). Should I delete the 30-day Vivado_ML_Enterprise_Edition evaluation license and all other licenses except the OEM _7K325T_DesignEd license? What version of Vivado Design Edition should I use and where to download? Currently only the Vivado_ML_Enterprise Edition can see the Genesys2 board.
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