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Found 9 results

  1. I’m trying to debug a program Factorial.c on the Nexys A7 50T FPGA board using PlatformIO. I have procured its bitstream file from the GitHub repository. Shown below is the platformio.ini code: [env:swervolf_nexys] platform = chipsalliance board = swervolf_nexys framework = wd-riscv-sdk monitor_speed = 115200 board_build.bitstream_file = D:\STUDIES\NexysFiles\Nexys-A7-50T-OOB-2018.2-1\vivado_proj\Nexys-A7-50T-OOB.runs\impl_1\nexys50t.bit Shown below is the program code: #if defined(D_NEXYS_A7) #include <bsp_printf.h> #include <bsp_mem_map.h> #include <bsp_version.h> #else PRE_COMPILED_MSG("no platform was defined") #endif #include <psp_api.h> #define N 7 int main(void) { int fact = 1; int temp = N; while(temp > 0){ fact *= temp; temp -= 1; } uartInit(); // Initialize UART printfNexys("Factorial of %d: %d ", N, fact); } Using PlatformIO, the bitstream is uploaded successfully on the board: After clicking on “Run Debug”, the compilation is also done successfully: But the debug console fails with the following errors: My current driver used is: I have installed it using Zadig and have also tried reinstalling the driver but the same issue persists. Please help me resolve this issue.
  2. Hi, I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example Frequency resolution = sampling frequency/number of samples DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore, Expected frequency resolution = 1MHz/65536, however, measured frequency resolution =5MHz/65536 in Behavioral simulation (Vivado 2017) It does not matter what is the clock frequency of DDS compiler, the frequency resolution of the FFT remains at 5MHz/65536. But, in reality the frequency resolution is fixed by sample rate of input signals and the buffer size of FFT. So, my question is, why in FPGA the frequency resolution is fixed by the clock frequency of FFT rather than sample rate of the input signal. Help is much appreciated. Regards, Subash
  3. Hello. I believe similar questions are present on the forum before mine. But I specifically want to know aside from the peripherals difference (RAM, SDCard, VGA etc.), is it ideal to assume the HDL designs (except the peripherals IP) would be compatible with both of them if one is supported by some project. For instance, lowRISC has a guide based on Nexys for its core booting Linux (https://www.lowrisc.org/docs/untether-v0.2/fpga-demo) whereas SiFive E310 has been demonstrated on Arty. The LiteX project supports both the boards (at least from the code base it looks so). Can someone experienced with this please guide me. I'm inclined towards the Nexys version as most of the peripherals I would be interested in are present on board, but I certainly don't want to have limited capabilities for certain projects compared to Arty. Thanks
  4. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  5. I left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. The computer's device manager shows that something is plugged in, but Adept and Vivado are unable to recognize that a device is connected. I was planning to restore the board to it's default setting on Vivado by using a .bin file but received the following error message: "ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Common 17-39] 'open_hw_target' failed due to earlier err." I used a voltmeter to test the voltage across the on/off switch and was getting around 3.3V but now get 0.003V. When I tested the switches that control the on-board LEDS, the also produced around 0.003V. Is there a solution to help me with this as the board is brand new?
  6. Hi, I have a Nexys A7-100T board. I want to supply voltage using external battery pack for my measurement. But for my measurement setting,voltage supply line has 6.5Ω resistance.When I supplied 5 V to voltage supply line, FPGA coundn 't activated. I guessed the reason for activation problem is voltage drop. I supplied about 7.25 voltage so that voltage between battery’s positive terminal to the center pin of JP3 and the negative terminal to the pin labeled J12 is about 5 voltage.I checked the center pin of JP3 and the pin of J12 is about 5V. But I coundn 't activated. Why coundn 't I activate Nexys A7-100T? Circuit_schematic.bmp
  7. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  8. logansam

    Nexys FPGA board

    From the album: Nexys FPGA SNES

    http://danstrother.com/fpga-nes/
  9. logansam

    FPGA NES

    From the album: Nexys FPGA SNES

    http://danstrother.com/fpga-nes/