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  1. I am working with a custom-made FMC (HPC) that attaches to a Genesys2 board with VADJ=3.3V. Among various signals, I have two LVDS_25 clock inputs on the pairs L25/K25 (FMC pins K4/K5) and F12/E13 (FMC pins K28/K29): set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVDS_25} [get_ports clk0_p]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2] set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVDS_25} [get_ports clk0_n]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2] create_clock -period 9.523 -name clk0_105mhz [get_ports clk0_p]; set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS_25} [get_ports clk1_p]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06] set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS_25} [get_ports clk1_n]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06] create_clock -period 9.523 -name clk1_105mhz [get_ports clk1_p]; To my understanding, both pin pairs are clock-capable and Vivado synthesizes/implements without issues. The HB bank is powered by an external voltage of 3.3V from the FMC card. For sanity checking, I pass both clocks through IBUFGDSs... wire w_clk0_ibufg; IBUFGDS clk0_ibufgds_inst (.I(clk0_p), .IB(clk0_n), .O(w_clk0_ibufg)); wire w_clk1_ibufg; IBUFGDS clk1_ibufgds_inst (.I(clk1_p), .IB(clk1_n), .O(w_clk1_ibufg)); ...divide the clock and power a couple of LEDs to confirm signal availability: reg [25:0] r_clk0div = 0; reg [25:0] r_clk1div = 0; assign led[0] = r_clk0div[25]; assign led[1] = r_clk1div[25]; always @(posedge w_clk0_ibufg) begin r_clk0div <= r_clk0div + 1; end always @(posedge w_clk1_ibufg) begin r_clk1div <= r_clk1div + 1; end To my surprise, I see only led[0] blinking (with irregularities), but not led[1]. I see a LVDS signal on the FMC connector pins of both clock inputs. The signals are somewhat distorted (oscilloscope struggles to trigger at the proper period) and led[0] blinks irregularly at times. Due to reasons, the FMC is connected to the Genesys2 board by an 250mm cable [1]. My guess is that the additional connector introduces reflections and the cable attenuates the clock signals to a degree that the FPGA does not detect a LVDS signal. Is it really this "simple", or am I missing something? [1]
  2. Using a Genesys ZU board with a Xilinx FMC-105 board, I am attempting to connect a JTAG/TRACE probe using the JTAG header on the FMC. The probe reports TDO appears always high. I confirmed that the JTAG header on board (J28) works with a Xilinx probe, but does not work from the FMC. Examining the schematics I noticed that FMC_TDO is tied to JTAG_TDO and FPGA_TDI is tied to JTAG_TDI. That seems wrong to me. I was expecting that the FMC_TDO would go to the FTDI/USB TDI. I know the schematic page is omitted because of licensing issues, but can you confirm that the JTAG chain is functional from the FMC side.
  3. Hello everybody, I am building a Petalinux v2019.1 project to save images using v4l2 driver. The pipeline is simple which includes Pcam-> MIPI csi2 rx subsystem -> sensor Demosaic -> video frame buffer write When I use v4l2-ctl -d /dev/video0 --set-fmt-video=widhth=1280,height=720,pixelformat=RGB24 --stream-mmap --stream-count=1 --stream-to = test.raw to save the Image. test.raw file is saved however it is of size zero. When asked on forums it turned out that there is issue with output format. According to Pcam reference manual it supports RAW10, RGB565 , CCIR656, YUV422/420, YCbCr422 and JPEG compression. Unfortunately MIPI IP core driver doesn't support RAW 10 format. Is there a way I can change PCam output format to RAW8 ? Thanks in Advance.
  4. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high throughput and low latency on this board? Is it possible to extend the board with PCIe? To get the full Ethernet capacity, could you please advise if purchasing a TEMAC IP license is advised and at what price? What are the alternative options and industry standards? Many thanks YM
  5. I have an I/0 limited application and looking through the Digilent catalog I find several boards with FMC/HPC connectors and am wondering if the pins can be used as general I/O ports. For example, the Genesys-2 board. If so, can you recommend a mezzanine card to communicate signals to and from the FMC connector? Cheers,
  6. I'm trying to use Pcam FMC with a ZCU102. I've looked through this post so I know there may be a way forward by editing the netlist using post synthesis constraining. Because the I2C switch select lines are grounded on the ZCU102, I can only communicate with CAMA so going to use this as a one camera interface. I've also verified the IO requirements and other architecture requirements. So far, I don't see anything stopping me from using to interface with camera A with a ZCU102. However, I want to use the MIPI D-PHY Xilinx IP but need help with the configuration. Looking through the timing.xdc in the reference project, the data rate appears to be 420Mbps. Is this correct? What are the recommended/correct settings? Please see screenshot. Any other advice on using this with a ZCU102 is appreciated.
  7. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  8. Hello, I'm designing a custom FMC board to use with my Genesys 2. Is there any informations about GTX and serdes pair length ? Thanks
  9. Designing a FMC Daughter Card to work with the Gensys2 Module. This will use all 10 Gb/s channels along with SysRef and Clk lines. Are there application notes available for such designs? Can you provide the track lengths from the FPGA to the FMC connector so that we can balance the overall track lengths on the combined boards. Any other advice welcome.