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Found 7 results

  1. Hello, I need help on a Basys2 board, that show incompresible characters when Adept runs at begin. Then I get this when it Initialize Chain (see below). You can see the error on attached file. The board is from an school laboratory and it is use by many students, so nobody know what happend to get this status in the board. ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.19 Adept Application Rev 2.4.2 Copyright © 2010 Loading board information... Initializing Scan Chain... Board information loaded. Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Initialization Failed. Regards Luis
  2. Hi I am working on Zedboard LED Demo but I cannot do the 13 step : Programming FPGA with Bit File. It seem to be an error when Zedboard use Microblade instead of ZynQ 7000 series. I also see some mistakes in step 11. The tutorial chooses processor is Microblade which not available when using Zedboard!. I need to run this example for testing my Board. Please help me. Link for the tutorial : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-led-demo/start\
  3. I have been following your "low_level_zmod_adc_dac" demo tutorial found at https://reference.digilentinc.com/reference/programmable-logic/eclypse-z7/low_level_zmod_adc_dac, and I believe there may be a typo. I copied the TCL commands to check out the project and received a "couldn't read file" error in the TCL command window. The command provided in the demo tutorial is set argv ""; source digilent-vivado-scripts/digilent-vivado-checkout.tcl, with all hypens. However, the scripts from the GIT digilent-vivado-scripts GIT project use underscores in the tcl filenames. Note that the example command shown on the digilent-vivado-scripts GIT project correctly shows the script filenames with underscores. I believe, "digilent-vivado-scripts/digilent-vivado-checkout.tcl" should be "digilent-vivado-scripts/digilent_vivado_checkout.tcl".
  4. Hello, I am having issues with my analog discovery 2. When I try accessing the device in the device manager of waveforms, I keep getting the same error code listed below. I have tried redownloading the waveforms software, but this hasn't fixed the issue. Any help would be greatly appreciated. Thanks for the help!
  5. I purchased a PMOD-BT2 recently and since (according to your documentation) the SPI connector uses the same power as the regular PMOD connector, I though I could just connect it via the SPI header (not supplied), for programming. Strangely enough, the FPGA board (a Nexys4-DDR) would not power up. An investigation reveals a strange fact: according to an ohm-meter the power on the SPI header is reversed compared to your documentation. I would appreciate it if someone from Digilent could confirm this from the PCB schematics and update your documentation ASAP, as well as issue an errata, because connecting the power the wrong way round has a habit of blowing things up.
  6. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  7. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.