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Found 6 results

  1. Hello, I'm trying to connect a JTAG-HS3 (Rev.A) with a Spartan-7 (XC7S6-1FTGB196C) using Vivado Lab Edition 2021.2 but Vivado keeps telling me that I should check cable connectivity and Spartan-7 cannot be found.I tried two HS3 to be sure it's not damaged. I tried speed down to 125kHz. A Xilinx platform cable USB II works fine with same cable (HS3 needs a extra pin header since HS3 and platform cable have different genders). VREF is at 3V3. TCK, TMS, TDI and TDO have all a 10k pull up. The levels of TCK and TDI look fine during startup (3V3) but drop down to 1V after a short while. Spartan-7's flash hasn't been written yet. Any idea what's wrong here? What pull ups/downs are needed by HS3? Thanks a lot for all your help in advance!
  2. I'm having trouble programming a XCKU060 with the JTAG-HS3. Occasionally it succeeds and programs correctly, maybe 1 in 10 tries, but mostly programming fails with "ERROR: [Labtools 27-3165] End of startup status: LOW" Using the Xilinx DLC9G JTAG adapter on the same board always succeeds in programming. Looking at a logic analyzer capture of the JTAG data there is a point where it looks like the TDI gets stuck high when the programming fails. It seems like there is some state or timing issue, but I'm not sure how to figure out what it is. I've tried different JTAG speeds, even down to 125Khz and it's always the same. Any help would be apricated. Thanks
  3. Jose Carmo


    Hi, I have a HS3 dongle that appears to have its EEPROM corrupted. The device enumerates with the FTDI VID:PID pair. Can you help? Thankx...
  4. Hello, I have used the digilent JTAG-HS3 programmer simultaneously with other device with FT232H chip and I have probably erased by accident the FT232 chip on Digilent module or there is a problem with drivers - the device is still recognized as Digilent USB serial converter by the system so I think is not damaged, but the cable is not visible in xilinx software. Could you please help me?
  5. Hello everyone, I have been trying to interface JTAG HS3 + JTAG UART with Adalm-Pluto using Xilinx vitis. I have exported .XSA file for zynq zc010 and tried to build an standalone application for simple Hello World program, but I'm facing an error while i try to debug as lauch hardware. I faced the following error. Error while launching program: fpga configuration failed. DONE PIN is not HIGH
  6. Hi, First thing first. I am a starter in the fpga custom design. I have done few simple projects codes in Digilent virtex 5 board but now circumstances requires me to get more IO pins. I will, in this section mention first what I am planning (English is not my first language sorry for any errors). 1) I am using XC6SLX9 2) Route the VCCAUX, VCCINT, GND, 100MHZ single ended clk. 3) Route out the JTAG pins (namely TMS, TDO, TDI, TCK) 4) I am using ISE 14.7 5) 1) I just want to generate gate signals. In this section I shall lay out what help I want. 1) Is what I have done enough to program the spartan 6 device via JTAG? (I know it will be volatile) 2) Can I program it using the JTAG HS3 cable? (someone said that I need the platform cable to program and HS3 only works with series 7 ics, but platform cable would cost too much for me at this moment) 3) For a 14pins (7 pins in 2 row) JTAG connector, what other routing I need to consider from the FPGA (except the 4 JTAG pins mentioned in the previous section) . Any other help or information that I need is extremely acknowledged. FYI: I am also attaching an approximate final outcome that I want.
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