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Found 6 results

  1. Hi, I have recently bought the Genesys Zu 5EV and i have some problems with the tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" i have tried to reproduce all point step by step but i have some errors and i am wondering if there is some problem on the guide or with the versions. Here are all steps i have followed and the problems/errors i get: Vivado part In the step "Add a Zynq UltraScale+ Processor to a Block Design" In the part that says "The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard." When they suggest to add a second clock, looks like it is not necessary, if I add it then I have an error afterwards about where to connect this pin. To solve this issue I have removed this clock (i assume is not necessary to have a second clock here). Tehrefore i have also avoid the part of "add a Concat IP to your block design, and manually connect it to the pl_ps_irq0 port." In step "Add GPIO Peripherals to a Block Design" part of AXI_GPIO_BUTTONS First i add the xdc file Genesys-ZU-5EV-D-Master.xdc for the contraints In the guide it says "_the button interface to “btn_tri_io[#]”, where # is a decimal number, counting up from zero. When finished, save the file_.". However the button on the Genesys-ZU-5EV-D-Master.xdc starts on 2 until 6 I have re-named the file as suggested in the guide However the guide says "In particular, the width of the GPIO interface must match the number of buttons available on the board." and i f i am not wrong in the genesys zu board there are 7 buttons not 5 (BTN0, BTN1, BTNL, BTNR, BTNU, BTND,BTNC) but the xdc file only defines 5, is this correct? In step Edit the Address Map Here the values are different that the ones of the guide, but i have checked that there is no Assigning an segment to address 0 to avoid errors as explained in the guide. is this correct? In step "Validate a Block Design" it shows an error in the pin saxihpc0_fdp_aclk Following the figures of the guide (even if they are not the same for the zynq ultrascate), I have connected the pin that produce the error (_saxishpc0_fdp_aclk_) to the pin _pl_clk0_ (clock) pin. Sfter that the validation is ok, is this correct? The validation now is ok, but it shows the following warning messages Vitis part In the "Create a New Application Project" When i have to select the Aplication project details. Which Processor should i use? In the guide the picture is different. Is it correct to use the first one _psu_cortexa53_0_ ? As suggested in the guide " Change the BTN_MASK and LED_MASK macros so that they contain a number of '1's equal to the number of buttons and leds connected to the GPIO peripherals in the hardware design." Here i assume is 5 for buttons and 4 for leds as i did it in the vivado part is this correct? how do i know the buttons and leds connected to the GPIO peripherals in the hardware design ? In the step "Launch a Vitis Baremetal Software Application" When i try to make _Run as → 1 Launch on Hardware (Single Application Debug)._ It pops up an error window. If i run with the option " Launch on emulator" looks like is working, but i do not knw how to test the buttons and leds there. Many thanks, log_build_vivado_project.txt
  2. Hi, I am trying to follow the HDMI for the Genesys ZU-5EV board as described here: I have and error in the "Launch the Vitis Baremetal Software Application" It looks like a path problem with the "/" and "\", which i guess is also related with the makefiles that the demos is using in 5ev_boot and 5ev_hdmi_demo_system. There is one line which clearly is not in my computer: XPFM_PATH = C:/Users/bvanca/Downloads/Zybo-Z7-20-HDMI-2020.1-1/hw/Genesys-ZU/sw/ws/5ev_hw_pf/export/5ev_hw_pf/5ev_hw_pf.xpfm I have tried to change this path, but i did not fine this file in the folder of the demo. I have also changed the path of the lscript.ld as i realize that was also wrong and after clean and build again i still have error, but this time there is almost no information. It seems that there is still an error in the make file After that i have tried to run the application and i get the following messages in the Tera Any idea on how to change the make files? should it work directly in the Genesys ZU-5EV board? Many thanks in advance Victor
  3. Hello, I have the Genesys ZU-3EG REV B board and would like to use it with the latest Xilinx tools - Vivado/Vitis 2021.1. The git repository for the Hello World demo that I want to start with (branch 3eg/master) is apparently for the latest rev. D of the board and version 2020.1 of the Xilinx tools. Where can I find the Hello World git repo for Rev. B of the board and what is the migration path to use it with the latest Xilinx tools Vivado/Vitis 2021.1? Thanks in advance!
  4. Hello, according to the image from GenesysZu-3eg, I can see a HDMI Tx and Rx interface. Can I solder a tx and Rx HDMI port according to the schematic and use this connection? Can I have this support from Digilent? Is there any established circuit connection or just the design? Since it is not sure when 5ev will release, this kind of support will be really helpful.
  5. I attempted to load the ZMod ADC1410 A/D converter for the Genesys ZU3 board IP into my Vivado design (2019.2). However, the ADC1410 controller cannot be loaded into Vivado 2019.2 because the IP does not support the Genesys board. As a result, I have a AXI interface board for a board IP that won't load. Is there an update to the Vivado IP so that the AD board will work on Genesys ZU3?
  6. Is there any Linux SD card image for Genesys-ZU that will boot into Ubuntu ? Otherwise, is there any manual that can help to build the image?