JColvin

Hi @Klavs, I apologize for the delay. I have sent you a PM with some instructions. Thanks, JColvin

Hi @Leon.k, I apologize for the delay. Do you have any device attached to your JTAG HS3? In general, the device ID will be read as all f's like you found if there is not anything attached to the HS3. Additionally, are you only connected to the Arty A7 via the micro USB connector (and not have anything attached via 6-pin JTAG connector, J8)? I can't directly tell from your picture, but I presume the power supply used for the Arty is between 7 and 15V and you have the power selection set to regulated power? Thanks, JColvin

Hi @1bioKAT, The engineer best suited to answer your question is out on medical leave, but I wanted to let you know that we seen your question and have not forgotten it. Thanks, JColvin

HI @Leon.k, I apologize for the delay. What do you mean by lost contact? Is the board still successfully powered? Or do Adept and the Vivado Hardware Manager no longer detect the board? If the latter is the case, the two easy things to check would be to try a different USB port and a different USB cable. I'm not certain why reinstalling Adept would have made a change initially. Thanks, JColvin

Hi @hurricane, I have sent you a PM. Thanks, JColvin

Hi @Stefan0, I asked our layout engineer about this and they provided the following dimension details (attached as an image). Let me know if you have any questions about this. Thanks, JColvin

Hi @Lucifer, I have sent you a PM with some instructions. Thanks, JColvin

Hi @Lucifer, If it's still correctly being detected as the Digilent USB serial converter, then that is a good sign. Could you also see if the cable is successfully recognized by the Digilent Adept software, https://reference.digilentinc.com/reference/software/adept/start? Thanks, JColvin

Hi @Madhusudhan, I have sent you a PM with the instructions. Thanks, JColvin

Hi @Gabriel Degret, I've sent you a PM about this. Thanks, JColvin

Hi @jonpaolo02, I was able to get the WiFi IP working successfully on the Zedboard with Vivado and Vitis 2019.2 This is what I did to get to working : 1. Build Block Design as normal in Vivado 2019.2 (i.e., I followed the Getting Started with Pmod IPs, and used the latest Vivado library zip download from the Digilent GitHub). 2. Create the HDL wrapper for the block design, generate the bitstream, and export the hardware including the bitstream via the File->Export->Export Hardware option. This will create a .xsa file that Vitis uses. 3. Under the Tools option, choose Launch Vitis. 4. After Vitis has successfully launched, choose the "Create Platform Project" under the Project header in the middle of the GUI. Choose a name for it and click Next. 5. Choose "Create from hardware specification (XSA)", click Next, and then browse for the XSA file that Vivado created in step 2. Keep the operating system as standalone and processor as ps7_cortexa9_0. You can choose to keep the Generate boot components checked or unchecked, though I did not test the boot components on my project in the in the interest of having less variables to worry about. (Edit: I tried later to get the boot components working, though have been unsuccessful as of yet) 6. This will create the create the platform in Vitis. I right-clicked on the platform project and chose "Clean Project" followed by "Build Project"; I'm not certain if those steps are a required, though it doesn't hurt. 7. I then clicked on File->New->Application Project. I named the project and clicked Next. Under the "Select a platform from repository" tab, I selected the platform I named earlier (in this case, "Zed-WiFiSD-19-2") and clicked Next. I changed the language used to C++ and maintained the standalone OS on the ps7_cortexa9_0 CPU and clicked Next. I choose Empty Application (since that was the only option) and choose Finish. 8. From there, I followed the same procedure used in SDK 2019.1; i.e., I copied the HTTPServer stored in the [platform_name]->hw->drivers->PmodWIFIF_v1_0->examples folder to the src folder in the application project created in Step 7, and made the changes to deWebIOServerSrc.cpp and HTTPServerConfig.h. 9. At this point, the only thing missing is the .elf file in the application project so it can be successfully launched. I was able to get it generated within the (currently missing) Binaries folder by right clicking on the application project (I choose the one with the "_system" in it's name) and choosing "Clean Project" followed by "Build Project" once the former has finished. This generated the .elf file. 10. There was an error listed in the project that states the .elf for the FSBL was not found, but since the Generate Boot Components option was left unchecked, I ignored this error. After turning on the Zedboard and connecting to it via a serial terminal, I then clicked on the Xilinx tab, chose "Program FPGA", and then right-clicked on the application project and choose Run As->Launch on Hardware. Please let me know if you have any questions about this. Thanks, JColvin design_1_wrapper.xsa vitis_export_archive.ide.zip

@jonpaolo02, I used the master one via the green "Clone or Download" button. The release version looked like it was done prior to the small changes that were made. I'll ask to see if this updated version will get a formal release.

Hi @jonpaolo02 and @rzsmi, I apologize for the long delay. I was able to get the Pmod WiFi up and running on Vivado and SDK 2019.1 (on Windows 10) successfully. I needed to download the latest Vivado Library from the Digilent GitHub (https://github.com/Digilent/vivado-library) since some changes were made to the compilation order on the Pmod WiFi a few months ago, and made sure that I had Vivado choose that repository via the Settings->IP->Repository within the Project Manager on the right-hand side of the Vivado GUI. I have attached a picture of my Block Design that I used. Otherwise, within SDK for completeness sake, I created a blank c++ application, deleted the main.c that came with it, and copied over the HTTPServer (since it already includes the same materials as the WiFiScan) from the hw_platform in the examples folder to the src folder within the application, made the appropriate WiFi SSID and password changes in the HTTPServerConfig.h file. I also made some changes in the deWebIOServerSrc.cpp file to make sure the appropriate input and output pins were added to the PinPage.htm via the addPINs function. I will test this on Vivado 2019.2 and Vitis/SDK 2019.2 as well. Please let me know if you have any questions about this. Thanks, JColvin

Hi @rorymc, I have sent you a PM. Thanks, JColvin

Hi @skywalker, Which Digilent blog post were you looking at which linked to this forum thread? I know the Cmod A7 Resource Center in the Example Projects section links to this forum thread (after I got permission from zygot to do so), but I would like to make sure that our blog posts link to the correct information. Additionally, the reason you had to regenerate the bitstream for step 4 for the Cmod A7 OOB demo was because you were using Vivado 2018.3 when the release was designed for Vivado 2018.2. Thanks, JColvin

Hi @efkean, Are you taking into account the fact that the Pmod AD1 IP already converts the data into the 0 V to 3.3 V from the 12-bit range of 0 to 1024? The values you referenced on the Pmod AD1 IP are accurate provided that the AXI clock connected to the IP core is not faster than 100 MHz (as per the Readme on the Pmod AD1 IP core on our GitHub). If you wanted to just have the 0 to 1024 data, you would need to change the functions used in the main.c file (within the SDK project) to only call AD1_GetSample and not call AD1_RawToPhysical (and adjust the printf functions to use RawData variables rather than PhysicalData values) to get a similar result. Let me know if you have any questions about this. Thanks, JColvin

Hi @jerryOn, I have sent you a PM with some instructions. Thanks, JColvin

Hi @Constantine, I have sent you a PM with some instructions. Thanks, JColvin

Hi @Constantine, Which Digilent board do you have? Thanks, JColvin

Hi @Karsten, I have sent you a PM with instructions. Thanks, JColvin

Hi @efkean, Unfortunately (presuming I understand your question correctly), the serial terminals that are typically used with Xilinx SDK (Tera Term or the built-in serial terminal) do not have a plotting feature available, so you will not get the same user experience in this way. You would need to export the data to a different software such as Matlab or Octave. Alternatively, you can find a way to visualize the data through something like Python in a similar way that was done on this project. Thanks, JColvin

Hi @paoppe, We don't have a CAD file for the Cora Z7, though we do now have an image of the hole dimensions present on the Cora Z7 which should help. Please let us know if you have any other dimensions you are looking for. Thanks, JColvin

Hi @efkean, I would recommend taking a look at these two threads on our Forum (link1 link2) that discuss getting the Pmod AD1 running on a Zedboard. What do you mean when you said the analog values don't look like the Arduino's? That the values are different by a few millivolts, completely different voltage readings, different format, or something else? Thanks, JColvin

Thanks for sharing what you found!

Hi @AThomas, Which JTAG IC are you using? We at Digilent also like to keep track of the usage of the JTAG reprogramming application (and as the application re-flashes the chip, it's easy to ruin a number of devices unitentionally, much like how our JTAG devices become unrecognized in the first place). Thanks, JColvin