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Found 5 results

  1. Hey, I am using Cortex M1 soft core processor on Arty A7 100T using Vivado 2020.1 and successfully generated bitstream for simple AXI-Uartlite project and exported hardware xsa file, but when i tried to create a Application Project for the same using xsa file in Vitis 2020.1 the platform is getting created but the basic c/c++ application project creation is giving error as "Failed to call GENERATE_APP". Below is the Vitis log file for that error. Can someone help in debugging this error? Thanks 13:51:28 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 13:51:28 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 13:51:28 INFO : Launching XSCT server: xsct.bat -n -interactive D:\FPGA_Projects\Workspace\temp_xsdb_launch_script.tcl 13:51:28 INFO : XSCT server has started successfully. 13:51:28 INFO : Registering command handlers for Vitis TCF services 13:51:29 INFO : plnx-install-location is set to '' 13:51:29 INFO : Successfully done setting XSCT server connection channel 13:51:29 INFO : Successfully done query RDI_DATADIR 13:51:29 INFO : Successfully done setting workspace for the tool. 13:51:29 INFO : Restoring global repository preferences: C:\Users\vybha\Documents\AT472-BU-98000-r0p1-00rel0\vivado\Arm_sw_repository 13:51:31 INFO : Platform repository initialization has completed. 13:52:35 INFO : Result from executing command 'getProjects': Microblaze_uart_wrapper;arty_uart1_wrapper;arty_uart_wrapper;arty_uart_wrapper_1;arty_uart_wrapper_2;cortex_m1_uart_wrapper;design_1_wrapper;mblz_uart_gpio_wrapper;mblz_uart_gpio_wrapper_1;mblz_uart_gpio_wrapper_2;zynq_uart_wrapper 13:52:35 INFO : Result from executing command 'getPlatforms': Microblaze_uart_wrapper|D:/FPGA_Projects/Workspace/Microblaze_uart_wrapper/export/Microblaze_uart_wrapper/Microblaze_uart_wrapper.xpfm;arty_uart1_wrapper|D:/FPGA_Projects/Workspace/arty_uart1_wrapper/export/arty_uart1_wrapper/arty_uart1_wrapper.xpfm;arty_uart_wrapper_1|D:/FPGA_Projects/Workspace/arty_uart_wrapper_1/export/arty_uart_wrapper_1/arty_uart_wrapper_1.xpfm;arty_uart_wrapper_2|D:/FPGA_Projects/Workspace/arty_uart_wrapper_2/export/arty_uart_wrapper_2/arty_uart_wrapper_2.xpfm;arty_uart_wrapper|D:/FPGA_Projects/Workspace/arty_uart_wrapper/export/arty_uart_wrapper/arty_uart_wrapper.xpfm;design_1_wrapper|D:/FPGA_Projects/Workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm;mblz_uart_gpio_wrapper_1|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_1/export/mblz_uart_gpio_wrapper_1/mblz_uart_gpio_wrapper_1.xpfm;mblz_uart_gpio_wrapper_2|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_2/export/mblz_uart_gpio_wrapper_2/mblz_uart_gpio_wrapper_2.xpfm;mblz_uart_gpio_wrapper|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper/export/mblz_uart_gpio_wrapper/mblz_uart_gpio_wrapper.xpfm;zynq_uart_wrapper|D:/FPGA_Projects/Workspace/zynq_uart_wrapper/export/zynq_uart_wrapper/zynq_uart_wrapper.xpfm 13:52:35 INFO : Platform 'cortex_m1_uart_wrapper' is added to custom repositories. 13:52:36 ERROR : Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. 13:52:36 ERROR : java.lang.RuntimeException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdk.xsdb.XsdbCommandUtils.handleResult(XsdbCommandUtils.java:387) at com.xilinx.sdk.xsdb.XsdbCommandUtils.executeAndRespond(XsdbCommandUtils.java:325) at com.xilinx.sdx.sdk.core.gen.CTemplateGen.generate(CTemplateGen.java:105) at com.xilinx.sdx.sdk.core.gen.CppTemplateGen.generate(CppTemplateGen.java:53) at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:93) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) 13:52:36 ERROR : Failed to create application project org.eclipse.core.runtime.CoreException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:150) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.executeInternal(SdkAppCreationHandler.java:75) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.lambda$1(SdkAppCreationHandler.java:67) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2311) 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references'
  2. I'm working with ARTY-A7 FPGA board and ADEPT v2.19.2 in Windows 10. At first, the system often lost contact with the board, but after reinstalling digilent.adept.system_v2.19.2, the connection was restored. Now reinstalling no longer helps. What can be a reason?
  3. Hello everyone! I am trying to program my Arty-7 A35T FPGA using OLIMEX-ARM-USB-TINY-H, can I do this or not? If yes then How?
  4. Hi, I'm relatively new to using Vivado with the Digilent boards. I have an Arty Z7-20 and started using it with Vivado 2019.1. I want to move on to Vivado 2020.1. When I originally installed 2019.1 I downloaded the Digilent vivado-library-v2019.1 from here https://github.com/Digilent/vivado-library/releases There does not seem to be a library v2020.1, v2019.1 seems to be the latest. Can I use library v2019.1 with Vivado 2020.1 or is there another way to achieve this? Thanks for your help!
  5. Hi, I am using Arty 7 to generate clock with different frequency. I wanted to save this data in my PC .since baud rate is 115200 and i am generating clock with 5MHZ ie at Rate of 5mbps. here speed of generation and data transfer are not same,speed of data transfer is much less than generation. please suggest me how can I save the data which i am genereting at same time.should I use ethernet for It?
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