JColvin

Hi @adelcastillo@spacevector.c, Potentially, yes. I don't personally know the full details behind the NDA, but I do know that we offer a licensing option. I have sent you a DM with the appropriate Digilent contact who will be able to provide you more details on this. Thanks, JColvin

Hi @adelcastillo@spacevector.c, I apologize for the delay. Digilent does not typically provide this schematic. Thanks, JColvin

Hi @bill v, Thank you sharing what you found!

Hi @zygot, In the interest of clarifying your question, are you wanting to configure and control aspects of the connected SYZYGY module and the hardware on the Eclypse Z7 that are volatile? Or are you looking to make different configurations become volatile? The phrasing of your question is a little difficult to interpret. Thanks, JColvin

Hi @jrochette, I've sent you a message with some instructions. Thanks, JColvin

Hi @armandomisista, I've sent you a PM with some instructions, though I am not certain if they will work for your situation. Thanks, JColvin

Hi @Samsonnn, I have sent you a PM. Thanks, JColvin

Sent

Hi @svaughn442, We don't have board files specifically for the Pynq Z1, though you can use the board files for the Arty Z7-20 which is a very similar board in terms of both specifications and layout. Please note that all support and materials for the Pynq-Z1 board are located on http://www.pynq.io/. Let me know if you have any questions. Thanks, JColvin

Hi @Siriusly?, I have sent you a PM with some instructions. Thank you, JColvin

Hi @PFuchs, I apologize for the delay; I have responded to your email that you previously sent to the Digilent Sales department with the needed details. Thank you, JColvin

Hi @armandomisista, Can you let me know some more details on how the JTAG HS2 became broken? I and another engineer I asked about this have never heard of it failing so badly that the FTDI chip needed replaced. The EEPROM is separate from the FTDI chip though so if only the FTDI chip was replaced the module should still be fine. Thanks, JColvin

Hi @hendog82, I have asked some other engineers for their input on this. Thank you, JColvin

Hi @Mark1, I have sent you a PM with some instructions. Thanks, JColvin

Hi @KKING, We are in the process of updating the standard; I'll let you know once it goes through. Thanks, JColvin

Hi @KKING, I believe we are on board with adding a Type 6A to the standard, though we do have a couple of questions/points that we would like your (or anybody reading this thread) feedback on as a customer. The main drawback against creating a Type 6A at the moment is that if pre-defined GPIO lines are added (I presume you are needing more than two of these GPIO lines since the standard as it currently stands allows for two alternate signals, such as an interrupt and a reset line, to be used in place of the No Connects on pins 1 and 2 on the Pmod header) the ability to daisy chain different I2C modules will become difficult. In principle, if all of the extra GPIO signals were only used on the bottom row of the Pmod header, you could still daisy chain I2C modules by treating the top header row as just Type 6, though that isn't necessarily following the spirit of being able to daisy-chain multiple modules together if you ignore half of the pins. Do you (or anybody else that happens to be reading this thread) have an opinion on this? Additionally, do you think the pass-through pins on header pins 1 and 2 would still be needed on the Type 6A, for the top row or to be included on the bottom row? Thank you, JColvin

Hi @KKING, I have formally put in the request for you. I hope to hear feedback regarding this change (though I can't imagine why this change would not be incorporated) in the next couple of days. Thanks, JColvin

Hi @KKING, I can put in the request for you. So I understand your question correctly, is this a request for this description to be formally added so that you can develop modules that conform to the Pmod Standard? Otherwise the Digilent system boards with the two row Pmod headers are GPIO based so that they can readily support a variety of protocols. Thank you, JColvin

Ok, I have sent you a direct message with the contact information.

Hi @WojtekSkulski, We do not share this exact configuration, though if you wish I can put you in contact with the appropriate representative at Digilent with regards to licensing our FTDI solution. Thanks, JColvin

Hi @Toladar, I don't know for certain if this is built into the Linux version of the WaveForms app, though it is in the Windows version where you can reprogram the EEPROM directly from WaveForms. Essentially, when you open up WaveForms and go to select your device in the Device Manager, there would be a "My device is not listed button" that will walk you through the reprogramming process. This is shown more directly in this specific post here in step 3: https://forum.digilentinc.com/topic/35-analog-discovery-troubleshooting/?do=findComment&comment=53880. Are you able to successfully reprogram in the EEPROM through that method? Thanks, JColvin

Hi @Brent, I apologize for the delay. The two main hurdles to doing this on a Mac are the generation of the bitstream which we can't assist with since we use Xilinx's Vivado software to do this, though it sounds like you have that aspect covered, and the loading of the bitstream onto the FPGA itself. Digilent does not have any solution for you with the second half since our Adept software which would readily facilitate loading a bitstream onto a supported FPGA (such as the Basys 3) is not compatible with OSX (though it is with Windows and Linux). I did request some higher-ups at Digilent to consider making Adept compatible with OSX, though that's about all the sway I have is the requesting portion. One alternate solution you might be able to do is set up a remote desktop that students can connect to since (I think) it is possible to enable talking to other serial ports based on the last post in this thread: https://community.spiceworks.com/topic/999865-com-port-trouble-with-remote-desktop. I don't know how that will play between different operating systems (and will be pretty slow and painful if multiple students are using it simultaneously), but it is an option. Realistically though, a VM will be the way to go at least with regards to students doing their own development within Vivado. Thanks, JColvin

Hi @julienV, I am a little confused. Do you perhaps mean SMT1 rather than fmt1? Or, I suppose more specifically, which Digilent board are you working with? I'm not certain which recovery procedure you are referring to since the one I am thinking of would have been sent via direct message and not posted (at least as far as I am aware of). Thanks, JColvin

Hi @PeterT, I have sent you a PM with the contact information. Thanks, JColvin

That is correct, the Errors will be what is prevented Vivado from generating the bitstream, not the Warnings. Thanks, JColvin