JColvin

Hi @KKING, So much for the review process on Digilent's end. I'll get it updated today. Thank you, JColvin

Hi @specpro30, Turns out I was wrong on my comment about being able to use newer versions of the Vivado library and still have them work on older versions Vivado/SDK; that particular statement is only true for modules/IPs that are compiling correctly, or at least when I ran the SD project in 2019.1 with the v2020.1 library, I encountered similar errors in SDK 2019.1 that I was not able to readily resolve. I apologize for the confusion; I'll edit my old post to avoid confusing future readers. After changing the IP repository back to the local master (and regenerating the bitstream just in case) I was then able to build the SDK project without any issues. Please let me know if you have any questions about this. Thanks, JColvin

Hi @Marco Jassmann, I apologize for the delay. I have sent you a PM. Thanks, JColvin

Hi @KKING, I have updated the Pmod page with the new Pmod Interface Specification 1.3.0 that includes Type 6A. I'm also in the process of updating the individual Pmod pages to list which Digilent Pmods conform to 1.3.0. Thanks, JColvin

Hi @specpro30, I attached a pdf of block design (the exported design itself is too large to attach in the Forum) that I used to create the SDK project I linked earlier. I followed the 2020.1 guide to create this block design in 2019.1, though you can also follow the 2018.2 guide; either way, ignore the bit at the beginning of every guide that says to download a particular version of Digilent's vivado-library; as long as the library version you have matches or is newer than the Vivado version you have (and the IP on the newer vivado-library successfully builds on that newer version), that'll be all you need. Let me know if you have any questions. Thanks, JColvin A7100-PmodSD-BD.pdf

Hi @Behnam I have sent you a PM with the contact information. Thanks, JColvin

Hi @Behnam, I have sent you a PM. Thanks, JColvin

Hi @specpro30, I think the Pmod SD has not been updated to work with the Vivado and Vitis 2020.1, or at least I have not been able to get the project to successfully build on Vitis even with the updated library available on our GitHub here: https://github.com/Digilent/vivado-library/tree/v2020.1. Our content creator is looking into what needs to be changed in the Makefile. The archived project was probably made for a different board and had the interrupt controller on Microblaze enabled; I personally never use the archived projects for any of our Pmods. Thanks, JColvin

Hi @Marco Jassmann, Is this also with the JTAG HS3? Thanks, JColvin

Hi @Shiv, What values do you measure across the capacitors that were mentioned in this specific post? Do the power good LED light up when you connect a 12V power supply and turn on the Zedboard? Is the board detected by your operating system? What revision of the Zedboard do you have? Thanks, JColvin

Hi @Sanyika, I apologize; the updated libraries are available here: https://github.com/Digilent/vivado-library/tree/v2020.1. I know the 2020.1 version of the Digilent Vivado library is being updated though so I'm hesitant to link to one of the branches in the tutorial. I attempted to run this project as well in 2020.1, but got the same errors you did, so I believe the Pmod SD has not yet been updated to work with 2020.1 and Vitis (as you can see from the makefile errors in Vitis). I am not certain when it will be updated, though I do know that I successfully created and ran a Pmod SD project the other day with Vivado 2019.1. Thank you, JColvin

Hi @dohnalik, I have sent you a PM. Thanks, JColvin

Hi @Amirr, I have sent you a message about this. Thanks, JColvin

Hi @patrick79, I have sent you a message on this topic as well. Thanks, JColvin

Hi @specpro30, Potentially; I added in the DDR memory on my block design because I recall needing the external memory in order to handle the Pmod SD libraries. It may be possible to instead increase the local memory of Microblaze during it's Block Automation and successfully use the Pmod SD, but I have not attempted this. A guide on how you can do this in Vivado is available on our Wiki here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-pmod-ips; it's for Vivado 2020.1 (and correspondingly Vitis rather than SDK) but the Vivado implementation will be the same for running a Microblaze project without DDR. Let me know if you have any questions. Thanks, JColvin

Hi @Sanyika, What clock frequency do you have on the clk_out1 on your Clocking Wizard IP? I also don't usually clone the Pmod IPs from GitHub but instead follow the guide that we have on our Wiki here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-pmod-ips. Thanks, JColvin

Hi @specpro30, Could you attach a picture of your block design? I have attached my working SDK archive for the Arty A7 100T with the Pmod SD which another co-worker confirmed built on their machine (they launched SDK to the unzipped version of the folder, then imported the projects, and were able to successfully able to have the project build). Thank you, JColvin PmodSD-191-A7100-SDK.zip

Hi @specpro30, Oh I see. You'll actually need to create an empty C++ application rather than a C application as per the Pmod SD IP: https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodSD_v1_0 since that is what the material is based on. I was successfully able to get the Pmod SD demo running on an Arty A7 100T on Vivado 2019.1 at least. Let me know how this goes. Thanks, JColvin

Hi @specpro30, The warnings about different hardware you can ignore. I'll need to re-run this particular project to confirm, but I believe you will need to regenerate the BSP sources (right click on system.mss in the _bsp folder) and then rebuild the project (Project tab at the top of the window->Build All) in SDK to have that error be corrected. Thanks, JColvin

Zygot is correct. Unless otherwise noted directly on the project sources, the material on the Digilent GitHub follow the MIT license which we have available for viewing here: https://github.com/Digilent/licenses/blob/master/mit/License.txt. Thanks, JColvin

Hi @rvxprj, I would probably recommend taking a look at the Out-of-Box demo for the Nexys A7 then; this and other demos are available in the Nexys A7 Resource Center: https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start#example_projects. Let me know if you have any questions. Thanks, JColvin

Hi @KKING, I apologize. I had submitted the changes for review, but didn't receive feedback/changes on them so it slipped off the radar. I sent i to our content manager who handles formal documentation today and they said they should have the formal PDF version completed by early next week. I will let you know as soon as I hear it is completed and uploaded to the site, though you realistically start saying it is formally complaint now and point any customer to this thread who asks for verification. Thank you, JColvin

The Forum was updated again yesterday and unlike previous updates, this one introduced a change to the visual layout. We will be tweaking the visual pallet and layout over the next few days.

Hi @Greatzwall, It's posted in the Project Vault, https://forum.digilentinc.com/forum/16-project-vault/, which is the intended place to post completed projects. Thanks, JColvin

Welcome to the Forums @Sridhar!