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  1. Hi there! I'm an electrical engineering student and my group has been thrown in cold water: We have to do an SPI Project where we connect a PMOD-Mic3 to our Basys3 Board and measure the frequencies of sounds by giving the Mic signal out to the onboard LEDs. A lot of LEDs have to light up when the frequency is high (over 500 Hz) and less when the frequency gets lower. [We have to create a Vivado VHDL Project.] We have huge problems understanding the core of the exercise. So far, after hours of research, we were not succesful with anything but especially: Establishing SPI-Communication (Master-Slave) Creating working shift-registers Our question is: has anyone done anything like that and can provide us with tipps/tricks or even a working examplary code? We value copyright and would never copy your work, we just need an idea as we have never dealt with FPGAs, VHDL or SPI before. We would appreciate every answer, thank you all a lot in advance! Your ElectricalEngStudent :)
  2. OscarW

    Pmod issue

    Hello, I am using a pmod gps module and corresponding IP in vivado on a zedboard. My project uses the pps pulse generated by the gps module for timing and internal sync not very relevant to the question. But I also want to connect the IP, is there any way of branching the signal from the auto generated interface made by the board specification? If not, as mentioned in this thread from 2018, making ports manually through the contraints file and paring those to pin pmod_out_pin(1-4)_t? I get errors when leaving pmod_out_pinX_o and _i not connected, should these be shorted to the _t pin/ground/vcc?
  3. Hi, I'm trying to use the PMODs on the Cora Z7-10 to accept high-speed single ended signals from another board I am making. In the reference manual for this device it says: So my question is in regards to proper grounding here. If I have a pair JA1_P and JA1_N and want to use JA1_P as the single-ended input. It says I should drive JA1_N low on in the FPGA fabric, but do I also need to connect the output of that to ground (it kind of seems like I should)? I'm perhaps a little worried about ground spikes, so if I do, should I put a series resistor in with it? Will this affect the single-ended speed potential? My data rate is ~500Mbps on each line.
  4. Hi, I am trying to make a project where I can receive a digital data and store it in DDR memory, I want to ask how can I connect one of the HP PMOD port let say JC on Zyboz7 board with an external source ? Thanks
  5. YakirP

    Pmod wifi SDK problem

    Hi i'm using Vivado 2018.2 + Zedboard, my goal is to use the WiFiScan from the examples attached to Pmod WiFi folder. i have build the project in vivado section and exported it to SDK at that point i'm creating new application project, choose C++ project and select finish. i'm getting the following errors: flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem thanks for the help
  6. Greetings, I am trying to run the example code of SD PMOD on my Nexys4 DDR FPGA. I followed the tutorial to generate the hardware but when I move to Vitis and try to compile SD card example, it throws me the following error message: Checking for BSP changes to sync application flags for project 'sd_app'... 15:49:33 ERROR : Failed to openhw "/home/pmod_sd_wrapper/export/pmod_sd_wrapper/hw/pmod_sd_wrapper.xsa" Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors. 15:49:33 ERROR : Failed to update application flags from BSP for 'sd_app'. Reason: null I have seen other people having the same issue at other posts. The offered solution was to use Vivado/Vitis 2019 but unfortunately that's not possible for me. Is there any other workaround? PS: I used the vivado project provided at this post.
  7. I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. https://forum.digilentinc.com/topic/8943-pmod-as-input-and-output-gpio/ #Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }]; set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je_pin4_io }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je_pin7_io }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je_pin8_io }]; set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je_pin9_io }]; set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je_pin10_io }]; I am able to control the GPIO pins of port JF on the Zybo Z720 using the following code, how do I edit this so that I am able to turn on/off LEDs using the Pmod port JE instead. #include "xil_cache.h" #include "xparameters.h" #include "stdio.h" #include "xparameters.h" #include "xuartps.h" #include "xtime_l.h" #include "xgpiops.h" #include "sleep.h" #include "xil_io.h" #include "xil_types.h" #include "xil_printf.h" #include "sleep.h" #include "stdlib.h" #include "string.h" #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) #define TIMER_FREQ_HZ 100000000 #define MAX_WIDTH 320 #define MAX_HEIGHT 240 #define MAX_BUTTON 16 #ifdef __MICROBLAZE__ #define HOST_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_BASEADDR #define HostUart XUartLite #define HostUart_Config XUartLite_Config #define HostUart_CfgInitialize XUartLite_CfgInitialize #define HostUart_LookupConfig XUartLite_LookupConfig #define HostUart_Recv XUartLite_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->RegBaseAddr) #include "xuartlite.h" #include "xil_cache.h" #else #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #include "xuartps.h" #endif #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define BLOCK_SIZE 40 void startup(); XGpioPs_Config *ConfigPtr; XGpioPs output; int main() { startup(); while(1) { XGpioPs_WritePin(&output, 13, 1); //led on (pin 1,2,3,4) XGpioPs_WritePin(&output, 10, 1); XGpioPs_WritePin(&output, 11, 1); XGpioPs_WritePin(&output, 12, 1); } void startup(){ //initialize pins for JF ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID); XGpioPs_CfgInitialize(&output, ConfigPtr, ConfigPtr->BaseAddr); XGpioPs_SetDirectionPin(&output, 13, 1); XGpioPs_SetOutputEnablePin(&output, 13,1); //pin1 JF1 XGpioPs_SetDirectionPin(&output, 10, 1); XGpioPs_SetOutputEnablePin(&output, 10,1); //pin2 JF2 XGpioPs_SetDirectionPin(&output, 11, 1); XGpioPs_SetOutputEnablePin(&output, 11,1); //pin3 JF3 XGpioPs_SetDirectionPin(&output, 12, 1); XGpioPs_SetOutputEnablePin(&output, 12,1); //pin4 JF4 }
  8. Hi, this is my first try to interact with a chip, so please bear with me if my question is dumb. I'm using Basys3 with the pmod MIC3. The ADC gives back 4 leading zeros and 12 bits of data. I can get this out of pmod. But how to interpret this data? I understand the main principle of the ADC - I get a relative value between 0 and 2^12. The pmod's reference says that this value is representative of the volume and frequency. I assume that this is a kind of composite value, like X high bits are the frequency, and the rest are for volume, or similar - but couldn't find anything about such things. I was looking at all reference documentation and sample codes I could find, but maybe I was looking at wrong places. How do I get the volume and frequency separately out of the retrieved 12 bit value? Thanks
  9. Hello, Is there a product to connect all pins included in a female PMOD to a breadboard, so they can be accessed individually on the breadboard. thank you, Dan
  10. In Vivado (2021.2) I have created a new project for the ZedBoard that includes: MicroBlaze in microcontroller configuration with 128KiB local memory AXI interrupt controller AXI timer AXI GPIO (x2) MicroBlaze Debug Module UARTlite When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively): set_property PACKAGE_PIN Y10 [get_ports {uart_rtl_rxd}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {uart_rtl_txd}]; # "JA4" Now I get the following during placement ("Implementation/Place Design/Pin Planning/IO Standard"): [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs: uart_rtl_rxd (LVCMOS18, requiring VCCO=1.800) and sys_clock (LVCMOS33, requiring VCCO=3.300) All of the Pmod connections for the PL appear to be in Bank 13, which is 3.3v, so I am looking for a way to tell Vivado that I want "uart_rtl_rxd" and "uart_rtl_txd" to be 3.3V, and while I'm at it, add any necessary pull-ups/pull-downs. I found out about the "Pmod bridge" IP and installed the unpacked "vivado-library-zmod-v1-2091.1-2" into the IP repositories, and have tried to add "pmod bridge 1.1", routed the "tx_0" and "rx_0" from the UART Lite as I saw in one example, but can't figure out how to assign the "Pmod_out_0" I end up with to a specific Pmod connector. The tutorial at https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/2018.2 indicates that the "board" tab should have the Pmod interfaces listed, but they don't appear for the ZedBoard. I have attached the block design that removed the direct connection of the uartlite tx and rx signals to pins and added the Diligent Pmod Bridge IP as "tutorial_1.tcl". I am really out of my depth here. I will continue to seek answers via Google and forum searches, but any suggestions would be appreciated. Thanks. tutorial_1.tcl
  11. I setup 2 zybo boards, one sends data, and the other receives. The idea is to flip a switch on the sender to turn on an led on the receiving board. Th ey are configured the same, but one is coded to send, and the other to receive. Both boards are connected on two computers and can send/receive using the demo code from the digilent github. After modifying it to send the values from the switches, it does nothing. Here's what I've coded for the Send.txt and for the Receive.txt. Honestly, I'm not too sure what's going on in the code and am trying to make some sense from it. Any help would be appreciated.
  12. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &spi1 { is-decoded-cs = <0>; num-cs = <1>; status = "okay"; spidev@0x00 { compatible = "microchip,mcp25625"; spi-max-frequency = <10000000>; clocks = <&osc>; interrupt-parent = <&gpio0>; interrupts = <0 0x2>; reg = <0>; } }; I can even send and receive messages using `candump` and `cansend`, but the interface behaves strange together with some CAN libraries. E.g. Messages are sometimes not sent, when the library tries to send multiple messages without any delay between them. On the other hand, when I connect the PmodCAN to a RaspberryPi and use same said libraries, everything works fine. So the only difference I can see between the working Raspberry Pi and the "strange" behaving Zynq setup, is the manually defined device tree overlay you see above. Long story short: Is my device tree overlay for the PmodCAN correct, to use it together with the ZedBoard on the JE Pmod connector? Maybe there is even a template somewhere? Based on the issues I have, I suspect something might be wrong with the clock and frequency definitions ...
  13. Hello! I am still new to all of this so bare with me. I am creating a project that involves the JSTK2 PMOD and right now I want to test the PMOD on its own with the example codes on the Diligent GitHub before integrating to my system. However, I am getting stuck at generating a bitstream. I have already done this successfully in another RTL project with the KYPD PMOD and there were no problems. I will share a screenshot of my block design. I am using the Zybo Z7-10 and I am using Vivado 2021.1. I used this link to help me get started with my IP: https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start Like I mentioned this worked for the KYPD PMOD. Let me know if anything else is needed to help debug this. Here are the error messages: [DRC NSTD-1] Unspecified I/O Standard: 4 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. [DRC UCIO-1] Unconstrained Logical Port: 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. My assumption is that my constraints aren't defined properly but I am not sure where to go from there. Any advice/help would be greatly appreciated. Thank you!
  14. Kind of new to the world of FPGA tinkering. Just bought an ARTY board and the OLEDrgb pmod. Struggling to find some verilog code for the SPI driver, together with some simple demo that I could use with Vivado, perhaps a simple MicroBlaze code snipet that drives the display. I could then use this a base going forward. Does anyone recommend anything here? Thanks Steve
  15. Hello, all professionals There are 12 pins of every Pmod interface, but I discover only 10 of 12 pins are constrained to FPGA(as is described in the following screen-capture). Does that mean that the remaining two pins are not connected to FPGA?
  16. Hi, I had tried using the Pmod MTDS to build some simple projects by using the microblaze with Arty A7-35T. I had followed the "Getting Started with Digilent Pmod IPs" tutorial. The bitstream file was successfully generated and exported to the VITIS 2020.1. After I created an application project in the VITIS 2020.1, I copied the main.cc and MyDispDemo1.cc into the src folder as requested after read the README.txt. However, when I started to build the project, it failed. It seem like missing the library files for the MyDispDemo.cc. I had tried many methods, rebuild it, and try to export the bitstream file again to the VITIS 2020.1. However, the problem still exist. So, is there any steps I miss out? Kindly need some helps in order to make the Pmod MTDS works with the microblaze by using the Arty A7-35T. Thank you very much.
  17. Hello all, I'd like to connect a Pmod peripheral to the JF connector of Zybo z7-20, however, looks like the board files do not include this interface. When I open a new block design on Vivado, the "board" tab shows only JA through JE connectors. Do I have to manually map it? Maybe use the master xdc file? I'm using Vivado 2018.2 and the "new" board files from github. Thanks!
  18. Hi, I am currently working with the PmodCAN module and I am trying to make it work inside a bigger design with other AXI IPs. Unfortunately I can not find any documentation about the PmodCAN Vivado IP and the AXI address space. So I have some questions: 1. It is not clear to me, what the use case of the `AXI_LITE_GPIO` interface is. From what I can see, the PMOD interface is pre-defined to be used for the SPI communication with the MCP25625 IC; other SPI PMODS doesn't seem to need it either. I have the suspicion that some of the MCP25625 Pins can be configured as GPIOs in some way, but anything I thought would make sense, does not match with your provided C code examples. Which brings me to my second question. 2. Is there any documentation about the AXI address space and how to use it to configure, send and receive messages? I am currently trying to understand how the IP works by looking at the signals and the VHDL code. Unfortunately this approach is very time consuming and I could get things done much faster, if there is any documentation about the address space. Maybe I am just overlooking something here. To summarize, I would like to ask, if the intention behind the Vivado IP was primarily for demo purposes to use it from C code or not; should I rather implement my own IP to let it directly communicate with other AXI IPs?
  19. Has anyone had troubles with the PMOD SD Flash Internface where the 10k resistors are too big for the VCU118 board. We may have to create a new PMOD as the 10k causes excessive delay in the ramp above a certain frequency.
  20. Hi Digilent staff, and fellow forum members, Just wondering if you guys had considered making a USB HID -> PS/2 PMOD board? I was thinking of something like the circuit on the Nexys 3,4 boards which uses a PIC to convert a USB keyboard to PS/2 compatible signals. Would be handy for using newer USB keyboards/mice on PMOD socket equipped FPGA boards. PS/2 devices are becoming harder to find brand new. I (for one) would be interested in a few. Kind regards, Leslie
  21. I'm using Nexys A7-100T developmennt board. I'm having issues getting Pmod I2S2 to work. This is my test design: The clocking wizard creates a 11.289MHz master clock. The tranceiver module I'm using can be found here: https://forum.digikey.com/t/i2s-pmod-quick-start-vhdl/13065. It seems to be generating the serial and ws (word select) clocks properly. The problem is that I'm not getting any signal from the ADC. sdout pin stays high no matter what. Even if LINE IN was floating, I would expect zeros between left and right channel data. Is the Pmod faulty or am I missing something? The pinout looks fine too I connected headphones to the output and don't hear anything. Not even static. Please help me out on this I'll highly appreciate.
  22. Hello Recently I have purchased Digilent PMOD AD2. I want to interface PMOD AD2 with my Xilinx Spartan-6 LX45 FPGA board. For conversion of analog signal into digital format. Could you please help me to do this. should I have to write HDL code of I2C? what is maximum speed of operation of PMOD AD2? -- Thank you Gopal Krishna
  23. pedro_uno

    MRAM PMOD

    Hello, I need to develop software to control an Magnetoresistive RAM (MRAM). I searched for an MRAM PMOD and found this item out of stock. https://www.tindie.com/products/alliedcw/pmod-mram-nonvolatile-memory/ The picture shows a Digilent board but I do not find it on your website. Do you have any of these on hand? Why don't they show on your site? Pete
  24. Hi, everyone here. Now, I have tried with my Pmod AD1. I used the demo code provided by the Digilent, but the value shown in the Vitis Serial Terminal is different from the value I have seen in the multimeter. For example, when I insert my sensor A into the channel A0, the value shown in 2.56. The value shown in the multimeter is 2.9V. When I insert my sensor B into the channel A1, the value shown in the Vitis Serial Terminal is 1.08. The value shown in the multimeter is about 2.1V. When the sensor induced voltage exceeds 1.8V, the AD1 value returns back to 0. I think this diagram might tell me the reason. But I am not sure since I am new to FPGA & electronic and I don't quite understand the datasheet. (Link: https://www.analog.com/media/cn/technical-documentation/evaluation-documentation/AD7476A_7477A_7478A.pdf?_ga=2.196220652.1995249494.1621070558-1887244704.1616928603) Through comparing with the AD1 reading voltage and the multimeter voltage, i found there is an linear relationship between them. I made an excel file to show you guys the relationship. I suspected i need to add an additional voltage source but not sure as well. When I connects the Vcc to the D0 or D1, the serial terminal said 3.3V. I did not change anything in the demo code, is there anyway to allow the AD1 reading to be the same as the reading in the multimeter. Thanks Luke
  25. Greetings, It is my first time here so I apologise for my mistakes, I started a new project where I am using Nexys 3 board with a Pmod GPS module. I found a UART receiver/transmitter on the internet I wanted to test it out. So I connected the receiver to the USB UART Rx pin, in order to send from Serial COM data and then transmit back to the Serial COM the data I have sent. When I am sending a character from the serial, I receive the same character from the UART transmitter so I think that both of the components work fine. When I am sending the character A, I receive back the character A. My next step is to connect to the receiver the Rx pin of the GPS to read NMEA Sentences. In the manual it says that the GPS works at 9600 baud rate so I tune the code for 9600 baud rate. I start reading the NMEA but the serial out is garbages(I will post a photo for the results). In the top.v module a connect the two modules like this: receiver R1(clk, reset, RxD, data); // RxD is the serial output from GPS and data is the 8 bit output from UART // transmitter receives the 8 bit data from the above module transmitter T1(clk, reset, transmit, data, TxD); // data is the input and we send the serialized data back to the Tera Term serial COM Is there any mistake with the connection? Is there a problem with the baud rate? Because I have tested all the baud rates available but I had no result. This is the result with 115200 baud rate And these are the results for 9600 baud
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