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Found 4 results

  1. Hi, everyone here. Now, I have tried with my Pmod AD1. I used the demo code provided by the Digilent, but the value shown in the Vitis Serial Terminal is different from the value I have seen in the multimeter. For example, when I insert my sensor A into the channel A0, the value shown in 2.56. The value shown in the multimeter is 2.9V. When I insert my sensor B into the channel A1, the value shown in the Vitis Serial Terminal is 1.08. The value shown in the multimeter is about 2.1V. When the sensor induced voltage exceeds 1.8V, the AD1 value returns back to 0. I think this diagram might tell me the reason. But I am not sure since I am new to FPGA & electronic and I don't quite understand the datasheet. (Link: https://www.analog.com/media/cn/technical-documentation/evaluation-documentation/AD7476A_7477A_7478A.pdf?_ga=2.196220652.1995249494.1621070558-1887244704.1616928603) Through comparing with the AD1 reading voltage and the multimeter voltage, i found there is an linear relationship between them. I made an excel file to show you guys the relationship. I suspected i need to add an additional voltage source but not sure as well. When I connects the Vcc to the D0 or D1, the serial terminal said 3.3V. I did not change anything in the demo code, is there anyway to allow the AD1 reading to be the same as the reading in the multimeter. Thanks Luke
  2. Hi, I want to read analog data from ad1 pmod. For Vivado part, I use digilent pmod ips to connet fpga. For SDK part, I use AD1.h and AD1.c library in examples. My sensor sends to me analog values between 0-3.3V. (This is a heart rate ECG values). During using arduino, all heart beat data can be read. But I use same function for zedboard, Analog values doesnt look like arduino's. How I can configure and fix this problem? As you see ad1-zedboard connection as below.
  3. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  4. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance