JColvin

Hi @jmt, I have sent you a PM about this. Thanks, JColvin

Hi @victagayun, None of the sources that are posted on WaveFormsLive Resource Center or the Open' boards Resource Centers have been changed to make them unusable. What I would probably attempt to do would be to uninstall the Digilent Agent and then re-install it. Thanks, JColvin

Hi @mmachtey, Much of the Digilent staff is out of office these last couple of weeks of December, so it may be some time before we get a response and update for you. Thanks, JColvin

Hi @abaelen, I have reached out for this information, though the engineer who I typically get this information from is out of the office on vacation until 2021, so it will be some time before I have the details to share. Thank you, JColvin

Hi @dr12, No, a 3D CAD file has not been created for the Cora Z7. I will ask about it again, but am not anticipating on hearing that one will be created. Thanks, JColvin

Hi @Iceman2020, You can access the EEPROM through an executable provided by Digilent staff on a case-by-case basis which has a "wizard" to reset the EEPROM back to factory defaults by properly selecting the correct connected board and board type via the USB connector. Digilent otherwise does not provide details on the USB controller (which would normally be present on the intentionally blank page of the board's schematic). Alternatively, the EEPROM can be accessed via USB through other freely available 3rd party applications such as FT_PROG, though as hundreds of customers have learned, this can easily result in erasing or corrupting the embedded EEPROM such that the board is no longer detected or programmable by Xilinx software, usually turning the board into a paperweight. I have gone through the two documents again, hopefully having corrected the errors related to the naming of the FPGA part and it's associated RAM values this time and not listing the values for a different Artix 7 IC. Thank you, JColvin

Hi @sandeep, I apologize for the long delay I clearly missed this post; I have sent you a PM as well. Thanks, JColvin

Hi @Jorgep, Not at this time, no. It depends on what the boss says is a time priority. Hopefully it won't take long, but finding the (as far as I know) new bug and then making sure a proper fix is applied to this Pmod and the 50 other Pmod IPs will take some time. I would not expect it to be completed this week if that helps. And a number of the Digilent staff will take part or all of the week off next week, so it may be a bit of time before a fix is applied. I'm sorry that I don't have a more encouraging timeline to share. Thanks, JColvin

Hi @Jorgep, I confirmed this behavior after downloading Vivado 2020.2; I believe it's an issue with those lower four I/O pins on the Pmod header not being properly assigned, so I've asked the appropriate engineers to look into this since I don't think the IPs were changed much from their older versions, so this is likely Vivado expecting some more specialized syntax in the IP itself. Thanks, JColvin

Hi @San, I got confirmation that the source code I pointed to is the same source code used the the iOS and Android apps. When building the project, you will just need to specify the platform to be used or it will default to browser. Thanks, JColvin

The latest information that I have heard is that we are hoping for a late Q1 release, though this can vary depending on a number of factors. If it's any consolation, it's a later release date than Digilent would like it to be as well.

Hi @HOOKJANDRO, I will ask about this, though I do not know if this workshop is compatible with the 2020.1 tools; it was designed with Vivado 2017.4 and 2018.1. Thanks, JColvin

Hi all, I'm not sure what you mean getting the project build for iOS and Android. WaveFormsLivethat the OpenScope and OpenLogger uses is an externally hosted website. Local versions are hosted on an SD card that is then attached to one of the devices. The source code is and has been available on the Digilent GitHub: https://github.com/Digilent/openlogger, https://github.com/Digilent/openscope-mz and https://github.com/Digilent/waveforms-live. Yes. While WiFi is a nice feature (neither board has on board Ethernet), the end implementation was not ideal as you had to operate at much lower sample rates than is otherwise theoretically possible with the hardware.

Hi @RHa, I apologize for the delay. I have reached out to @Wyllyam about a potential update. Thank you, JColvin

Hi @JIBI3731, Are you using PetaLinux at all or Vitis HLS or something like that? Normally to creatte the appropriate file and program flash, you would follow these steps that are nicely outlined in this specific forum post here: https://forum.digilentinc.com/topic/5232-problem-with-how-to-store-your-sdk-project-in-spi-flash-tutorial/?do=findComment&comment=21569. These steps were written prior to the existence of Vitis, but the steps are still the same. Let me know if you have any questions. Thanks, JColvin

Hi @jeffdecola, Connecting GPIO between the Raspberry PI and a Pmod port on an Arty S7 can work since they both operate at 3.3V. Be sure to connect the grounds between the two boards though to better ensure you have a common reference voltage. I would also recommend using JC or JD on the Arty S7 as both of those Pmod ports have current limiting resistors to help prevent any problems (though I believe the gpio pins on both sets of boards are current limited to begin with). Thanks, JColvin

Hi @amehdi, I got confirmation that the USRB B205mini-i that Digilent sells and the one Ettus sells are the same board with the same specifications. You will be free to use the enclosure that Ettus sells separately, https://www.ettus.com/all-products/usrp-b205mini-i-enclosure/, on the module that Digilent sells. Based on the Ettus page for the enclosure, all it does is increase the safe operating temperature range. Thank you, JColvin

Despite our hopes and effort to create an innovative and low-cost T&M solution, we’ve received consistent negative feedback on the OpenScope MZ and OpenLogger regarding overall reliability that has led us to determine that it is not up to our high standards for our test and measurement products. Unfortunately, we are unable to fix many of the issues, so we have made the difficult decision to pull both products, and related accessories from our shelves. This will allow us to ensure we can continue to deliver on the Digilent brand promise and focus our efforts on expanding our popular and core line of Test and Measurement Products. The materials on this page will remain here as legacy sources. Any Digilent provided support for this material will be extremely limited at best. Thank you for understanding.

Hi @specpro30, It look me longer than I originally planned, but I made a couple of silent, screen capture only videos of creating a Microblaze block design and SDK project with the Pmod SD. Block Design Creation: https://www.youtube.com/watch?v=KQguA52kOO8 SDK Project Creation: https://www.youtube.com/watch?v=OYqnCVD4Zgs Let me know if you have any questions. Thanks, JColvin

Hi @specpro30, The lack of an active low reset on my design compared to your design is okay because there is a not gate included in my design, so your design is good to go in that regard. I had forgotten that implementation for the SD IP library uses SPI mode so the SPI clock needs to be a lot slower than what I provided in my design, so I'll need to rerun that on mine. I'm not sure why you have two Processor System Resets in your block design; I'm not what benefit this offers or how it got into your design. You also look like you included an AXI interrupt controller which is not needed. If you used my design directly, I think you'll probably need to refresh the BSP sources and build the project (ctrl+b) in SDK so Vivado/SDK isn't trying to use any filepaths that only exist on my computer. I'm seeing if I can get a simple video screen capture of my block design creation that doesn't require me having any video editing skills, software, or need me to point my phone camera at the screen for a terrible video. Thanks, JColvin

Hi @specpro30, I apologize for the confusion; I used Vivado 2019.1 and Xilinx SDK 2019.1. I'll edit my eariler post to prevent future confusion. Thanks, JColvin

Hi @redchenjs, I sent you a message. Thanks, JColvin

Hi @Marcel, What board are you using? I don't believe Digilent has any FT231X devices that I recall. Thanks, JColvin

I used 2019.1 for both Vivado and SDK (not Vitis). The vivado-library I used as my IP repository I downloaded from this page, https://github.com/Digilent/vivado-library. I believe you could also use the 2019.1 release version that is available on the right-hand side of the page, though I haven't specifically tested it since I have a local copy of the repository that I keep up to date with the master instead. Let me know if you have any questions or run into issues. Thanks, JColvin

Hi @specpro30, I'm not certain what else to suggest if refreshing the BSP sources and rebuilding the project in SDK does not make them go away. I found a way to upload the Vivado project archive that I used to create the SDK project I linked earlier; it is available for download here. Thanks, JColvin