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Found 6 results

  1. Hi all, I am an embedded software engineer trying to teach myself FPGA prototyping. I have been following the following tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi I am using the Nexys A7-100T board. I have followed the tutorial and validated the project, however when I go to implement the project I get critical timing errors. Below a few of the critical errors I get, and I have attached a screenshot of timing tab page. [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port btn_tri_io[0] can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74] [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port btn_tri_io[0] can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74] The tutorial is a great tutorial and does reference errors that may occur in some steps, however there is no reference to this error and what to do. I guess I have to modify some clock settings. Any help would be appreciated. Kind regards, Rochus
  2. Good Morning Folks! And it is indeed morning, it has been a long day, I started this journey yesterday morning. By way of introduction, and to set an expectation of my level of understanding, I'm an embedded software engineer just dipping a toe in the waters of FPGAs. So very new to this! After a few weeks of playing around with the Verilog and RTL I'm now interested in Microblaze and following (faithfully or perhaps more accurately blindly) the guidance in https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi Sadly, things have not gone as smoothly as I had hoped. Despite sticking closely to the guidance I keep ending up with the following warning, which ultimately leads to a routing error: [DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell processor_i/mig_7series_0/u_processor_mig_7series_0_2_mig/u_ddr2_infrastructure/gen_ui_extra_clocks.mmcm_i. The computed FVCO is 562.500 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 15.000, CLKIN1_PERIOD = 26.66667, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)). I'm using a Nexys 7-100T so substituting DDR2 where the guide refers to DDR3, otherwise it is all pretty much identical. I have the constraints file is in place and the vivado board file is also correct. The system clock is correctly named and uncommented. This is, of course, all generated by the various automated connection and block assistants, I barely had to do anything manually. Having researched this there are a fair number of reports of this but mostly seem to be related to older versions of Vivado or people not setting up Clocking Wizards correctly. The tutorial doesn't use a Clocking Wizard, instead relying on timing from the MIG IP and I'm using the current version of Vivado. I can see where these values are defined in the generated IP constraint files but I really don't think I should be in there changing stuff to make this work. One thing I have noted is that the MIG clock period is defaulted to 3333ps (approx 300MHz), I seem to recall that the reference guide for the board says 350MHz for DDR2 but the IP configurator won't let me go higher than the 300MHz, in any case the tutorial doesn't ask me to manually change anything so I've let that be what it is. Any pointers (in English rather than FPGAish) would be greatly appreciated. As for me, I'm going to bed and will face this again in the morning :-) Cheers, Y.
  3. Hey, we are working on a senior design project and to set up a xilinx zeboard we are looking to upload the hello world on to the zinq700. There is something wrong with the UART drivers and were getting this error above. Also pictured below. When we uninstall the driver that claims to be intsalled when we connect the device, and reinstall it. However the UART light remains yellow and ultimately shuts off as soon as we connect the comm port through the sdk, it the LED shuts off. Does anyone have any clue about this issue?
  4. k-k

    Beginner needs help

    Hello, I am an beginner and use a Zybo Z20 Board Vivado and Vitis. I tryed the Tutorial: Getting Started with Vivado and Vitis for Baremetal Software Projects - Digilent Reference (it works) Now i tryed to add a RTL-Block (VHDL) and connect it with the axi-gpio. Then i want to manipulate it using vitis and a c-code, a LED should shine. But it doesn't work. Is there a tutorial how to connect PL and PS? Can someone help me? Thanks
  5. Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following in "Message:" (attached) Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it. blinky.xpr Nexys-A7-100T-Master.xdc
  6. Hi, Where can I find a tutorial to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? I've searched everywhere, including this forum, and couldn't find a tutorial. I tried a tutorial on YouTube for the Artix 7, and I'm unable to generate a bitstream. I get this critical warning: [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port reset_0 can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["c:/Users/curti/XilinxProjectsCurtis/HelloWorld_hw/HelloWorld_hw.srcs/sources_1/bd/HelloWorld_design/ip/HelloWorld_design_rst_clk_wiz_1_100M_0/HelloWorld_design_rst_clk_wiz_1_100M_0_board.xdc":3] And I get these errors: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. [DRC UCIO-1] Unconstrained Logical Port: 3 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_0, diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. I'm a new user of Vitis, and relatively new to Vivado. Can anyone offer suggestions on how to correct the errors? Or, better yet, where can I find a tutorial that works to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? My thanks in advance for any suggestions, Curtis