thinkthinkthink

Oh you didn't install Kintex-7 support when you were prompted to by Vivado's installation procedure ? You can add it later without having to reinstall Vivado, if you're on windows look for Add Design Tools or Devices and then under 7 Series you can check the Kintex-7 box. Oh sorry, missed the part where you said you did check the Kintex-7 box at installation, it's still worth doing this to make sure it really was added.

Which version of Vivado did you install exactly, 2021.1 or 2021.2 ? Have you installed the board files while making a new project ? You can do so by clicking on the Refresh button in the lower left corner, then look for the Genesys2 board and press the Install button.

Yeah you're supposed to clone the repos and checkout the 20/Pcam-5C/Update branches. Here's a guide: Digilent FPGA Demo Git Repositories.

Here's the repo with the Keyboard Demo upgraded to Vivado 2020.1: Nexys A7 100T/Keyboard.

set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_rxd}]; # "JA3" set_property -dict { PACKAGE_PIN AA9 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_txd}]; # "JA4" Here, fixed your constraints for you, it's that easy.

It was already updated to 2021.1 on our github. Here's the Vivado repo branch and Vitis repo branch.

I'd go for an UltraScale+ device with Speed Grade at least -2 to ensure your project will pass timing analysis at those high sampling rates. On UltraScale/UltraScale+ architectures you might benefit from Xilinx's Machine Learning based Intelligent Design Runs that will help with Implementation. It might just be me but I honestly don't think 20k dollars/euros is enough of a budget for this.

Yeah those camera modules look about right. This is how I did it on the old ZYBO board: Piping OV7670 video to VGA output on ZYBO.

You can get an OV7670 camera module and some MTE cables and connect them to Pmod ports. Just be aware that you'll need maybe 2 or 3 Pmod ports for one camera module. I've managed to pull it off on the old ZYBO board.

Check out the ZedBoard's resource center.

Don't assume/believe anything until you've taken a good look at the schematics of the Pmod Shield and the Arty and its xdc. Some pins might have pullup resistors as they were meant to be used as I2C pins so make sure you're aware which are which. Also, you can find more details about the connectors on Arty's Reference Manual as well.

There's this guide I like by Lauri Võsandi called: Piping OV7670 video to VGA output on ZYBO. Dunno if it helps much but it might provide an insight into what you're trying to accomplish here.

Are you running multiple Vitis instances at the same time ? I've had some issues on multiple boards where I would start a debugging session in Vitis while my board was already connected to another Vitis debbuging session and that would cause a lot of annoyances. Maybe make sure you Disconnect your debugging session before starting a new one.

What development board are you working on and is your block design the same as in the FMC Pcam Adapter Demos ? Is the VADJ of your board set correctly to 2.5 V ? While debugging in SDK/Vitis is your processor getting stuck on a specific line most of the time ? How many Pcams do you have connected to the FMC Pcam Adapter ? Do the ribbon cables of the Pcams look ok ? Have you connected the Pcams correctly, are the ribbon cables inserted fully and tightened ? This project is fairly complex and so many things can go wrong with it. The configuration code shouldn't have any issues so I'm suspecting there's something wrong with your hardware unfortunately.

Used to happen for me as well, don't remember what fixed it, either ending the hw_server with Task Manager in Windows or restarting my PC. If you really want your board to program as fast as possible you can increase JTAG frequency to 30MHz in Vivado Hardware Manager. On kintex-7 and zynq ultrascale+ or above you'll see longer programming times since .bit files and etc. are bigger in size even on maximum JTAG frequency. The only problem with increasing JTAG frequency is if you have any ILAs in your design you should make sure that the clock at which those ILAs are running is at least 2.5 times higher than JTAG frequency according to Xilinx.

I'd recommend starting with Vivado and Vitis 2020.1 or 2021.1.

I'm still not familiar with all the intricacies of the PS, but you're getting your clocks from it so make sure the PS isn't in some idle state where everything is stopped including the PLLs, maybe put a while(1) loop at the end of your code. The PLLs inside the PS should still give out clock signals even if the ARM cores are in a parked state where they do nothing but dunno what's stopping them. Also try giving the ZYNQ 7000's technical reference manual a read too, it's called UG585 Zynq 7000 TRM, you might find something.

You don't need the GPIO IP, get rid of it, you just need to constrain the CTRL external input port to a switch or button in the board XDC file. It's probably because you connected the GPIO IP inputs/outputs to the switches that your CTRL port does nothing.

Disconnect from the Board flow tab and try again with manual constraints. Maybe it's also worth deleting the uartlite IP and adding it back again.

You can also try regenerating the bitstream after clearing IP cache from Tools->Settings->IP and/or manually constraining those pins in the board XDC file to your UART interface. It's pretty pointless to do any debugging if those pin connections haven't been made inside the FPGA. What I hope will happen is after you add an ILA to your design and regenerate the bitstream, Vivado will finally do its job properly during the synthesis and implementation phases.

Check your UART interface with an ILA. This should be the first thing to do when debugging in Vivado.

Nah, it's correct what you did with the external port and XDC file and it should have worked, maybe put an ILA on that line and see if it toggles correctly or try other switches maybe even the buttons. It could be that the switch is defective in which case maybe try cleaning it with some isopropylic alcohol.

Maybe you should try the new low-level IP that was made for the Zmod ADC/Scope: Zmod Scope Controller.

You're also limited by the processor to peripheral interconnect but then again you can just add another interconnect IP in your block design.

For the PS side you can use 2 XGpiops outputs and 1 Xgpiops input while on the PL side you'll have to either write your own VHDL/Verilog module that adds the 2 integers and outputs the sum into the Xgpiops input of the ZYNQ processing system or check if Xilinx offers IPs that perform additions/subtractions etc that come with your version of Vivado.